A state machine design problem

Hi,
I have the following VHDL code for a state machine:
type Output_State_t is (
State_a,
State_b,
State_c);
signal Output_State, Output_State_NS : Output_State_t ;
At a clocked process, there is code with the Output_State:
p1: process(Clock, Reset)
begin
if Reset then
Output_State
Reply to
Tianxiang Weng
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Hi,
I have found an error at another place and the listed code is right.
Weng
Reply to
Tianxiang Weng

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