I don't know if this is the right forum to post this to. If there's a forum that would be more appropriate for a question like this, please let me kno w.
Let's say for a moment that I need to build a Random Access Memory that con sists of 256 nybbles. An eight-bit address bus and a four-bit data bus conn ect the CPU to each of the 256 nybbles. To make things simple, let's assume that one control bit is also sent from the CPU to each of the 256 nybbles; if that bit is set, then the CPU writes to one of the nybbles; if that bit is not set, then one of the nybbles gets read by the CPU. So in the former case, whichever nybble has its address (a number from 0 to 255) match the contents of the address bus, reads the contents of the data bus to its inte rnal storage, and it's easy enough to imagine how I would do that. In the l atter case, each of the 255 nybbles whose address does NOT match the value on the address bus writes high impedance to the data bus, and the nybble th at DOES match the value on the address bus writes its contents to the data bus. How does it do that? How does it do that on the transistor level? An N
-channel MOSFET can write high impedance to a bus, but the only logical val ue it is any good at writing to a bus is a zero. And a P-channel MOSFET can write high impedance to a bus, but the only logical value is is any good a t writing to a bus is a one. So how can one of the mentioned nybbles be abl e to use MOSFETs of either or both variety to write to a bus when it might need to write any of those three values, a logical one, a logical zero, or high impedance?