Is there any software I can use to transform state machines in VHDL into drawings?

Questasim has a FSM debugger option that generates a graphical view of your state machine, but it's not always a great view for documentation purposes.

ware to transform the state machines in VHDL into drawings.

o drawings?

ur state machine, but it's not always a great view for documentation purpos es.

What I have been developing is a set of new hardware circuits that have bee n never used. I want to apply for patents with full state machines design d isclosed. For correctness, the state machines block diagrams should be cons istent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistence.

Weng

You could use

ote:

oftware to transform the state machines in VHDL into drawings.

into drawings?

your state machine, but it's not always a great view for documentation pur poses.

been never used. I want to apply for patents with full state machines desi gn disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistency.

Thomas Koenig, I reviewed the website

When reviewing a state machine design, it is easier to use state machine bl ock diagrams.

Thank you.

Weng

A codebase I look after puts $display statements in the code that print Graphviz code for each state in the state machine. The testbench exercises the code to pass through all the states. When run, you pipe the output into a .dot file and feed that into Graphviz, which will generate a PNG, SVG, PDF of the state transition diagram.

It's a hack, but it works well enough.

Theo

I believe the Sigasi editor has something like that:

Cheers, Guy.

TerosHDL plugin in VSCode has some rudimentary state-machine detection