Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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RLOC not working correctly in ISE 8.2 and 9.1?
I've been wondering if someone else has noticed that RLOCs does not seem to be working very well in ISE 8.2 and 9.1? Currently I'm experimenting with a project where the RLOCs are working ok for...
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17 years ago
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data2mem crash
Hi everyone, I just installed a new workstation, a Core2 duro running linux 64 bits. But I can use data2bram on it, it crashes every time. I've tested with both 8.2 and 9.1 (both with latest service...
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17 years ago
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Xilinx Spartan DCM jitter spectrum
Hello all, Does anyone has some numbers on the frequency spectrum of the jitter from a DCM? The datasheet says the DCM has a jitter of 100ps but I would like to know a bit more about the spectrum to...
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17 years ago
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Load V4 bitstream encryption key with XSVF
Hi. I want to load the bitstream encryption key on a V4FX board. Using IMPACT and a Xilinx download cable, I can successfully load it (together with a design file). However, my board doesn't normally...
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17 years ago
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Driving PLL from general I/O in Altera Cyclone
I am trying to deserialize a DDR signal in my Cyclone. For reasons I won't go into the DDR clock comes in off a general purpose I/O pin. I need a way of deserializing this signal, and want to increase...
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17 years ago
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XILINX ISE PAR error: CLK0_BUFG_INST is not placed
Dear all, while performing a Place and Route of a reconfigurable project (developed followinf the Early Access User Guide ug208) the par return this error: ERROR: CLock Buffer...
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17 years ago
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Xilinx CoreGen fifo - ngdbuild error
Hi everybody, since one day I am fighting with a Xilinx CoreGen IP. I am using Mentor Graphics Precision 2006a.101 and Xilinx ISE 9.1. I have a fifo IP generated the Xilinx CORE Generator. In my...
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17 years ago
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How best do I implement routing boxes in RTL?
In the design I have 256 3-bit registers, every time I need to read or write 16 of them (data_o0, 1, ...15). The read/write address is not totally random. For example, assuming that I arrange the...
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17 years ago
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CAN vhdl code document
hi, i have downloaded the CAN VHDL from opencores but am unable to understand the code. can anyone please tell me where i can get the document for that code. thanks ramesh.
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17 years ago
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odd warning in Xilinx ISE webpack
At the XST-synthesize stage, I'm getting this weird warning: "Property use_dsp48" is not applicable for this technology. I don't have anything in my code that I know of that calls for any such thing.....
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17 years ago
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Avnet Virtex-4 FX12 mini module
Hello, I have recently bought Avnet Virtex-4 FX12 mini module. I am trying to implement the Gigabit ethernet communication between the FPGA and the host PC. Can anyone give me some hints to get...
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17 years ago
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FPGA Vs ASIC design and implementation
Hi, Being familiar with FPGA design and implementation flow and illiterate with ASIC corresponding one. My question is the following what are the main similarities/differences between designing and...
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17 years ago
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using XIlinx impact in batch mode to generate EEPROM files
I am using xilinx tools in an unix system to do the P&R and generate the bit file. I am using a batch mode script to go through the steps. Currently I am running impact in gui mode ( either from UNIX...
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17 years ago
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Introducing picosecond delay between two output signals
Hi, I would like to know what are the common methods of introducing delays as low as 10ps between two outputs in an FPGA. I do not currently have a specific FPGA in mind. I am just looking for a...
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17 years ago
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DFF with clock and async-preset tied together
Assume we have this VHDL model process(sig) begin if ( sig = '1' ) then q
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17 years ago
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