Field-Programmable Gate Arrays

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Dual edge detection

Hi newsgroup, As shown in the VHDL code I am feeding two flip flop chains with the same input. The chains use complemen...
10 comments posted 19yrs
posted by ALuPin
10 comments posted 19yrs posted by ALuPin

Need help bringing up PCIe at the physical layer.

Gentlemen, Sorry if this is the wrong newsgroup for this. If someone can suggest a more appropriate forum, I'd be quite...
0 comments posted 19yrs
posted by jcr.nospam
0 comments posted 19yrs posted by jcr.nospam

Comunicate FPGA to Ethernet

Hi people, In last my design, I made a fpga board using IC xc3s400. Now i would like to modify it some following things...
0 comments posted 19yrs
posted by creativeperson8584
0 comments posted 19yrs posted by creativeperson8584

Xilinx: Case Statements

Xilinx has the ridiculous peculiarity of requiring sized cases in a case statement. I allow users of my module to set p...
0 comments posted 19yrs
posted by lingwitt
0 comments posted 19yrs posted by lingwitt

Heritage Data books!

hi, Pile of data books in search of a good home... I have a collection of perhaps 80 or 100 data books for various logi...
4 comments posted 19yrs
posted by jonathan.bromley
4 comments posted 19yrs posted by jonathan.bromley

Design report does not show BRAM usage

Hi all, I have created a peripheral and attached it to the OPB bus. This peripheral is composed of a controller and als...
9 comments posted 19yrs
posted by vbhanu
9 comments posted 19yrs posted by vbhanu

Are FPGAs go enough for clock dstribution

Hi, I have a PCB design with a FPGA and other devices that require a clock input. Is it a good idea to first feed a sin...
2 comments posted 19yrs
posted by ben.popoola
2 comments posted 19yrs posted by ben.popoola

ddr sdram controller

How can I get a ddr sdram controller for the MT46V16M16TG -75 micron chip. I want a controller without the plb or opb i...
5 comments posted 19yrs
posted by dhruvakshad
5 comments posted 19yrs posted by dhruvakshad

Addressing scheme in Block RAM

Hi People, I have generated a duap port RAM using a Xilinx Core generator . Port A is 32 x 32 and Port B is 8 x 128 The...
9 comments posted 19yrs
posted by get2venu
9 comments posted 19yrs posted by get2venu

Any Western NC VHDL Designers?

Is there anyone on this list looking for side work who lives in Western NC or possibly Eastern TN, North Western SC? Pl...
0 comments posted 19yrs
posted by Hawker{removethispart}
0 comments posted 19yrs posted by Hawker{removethispart}

XST 9.1 hates VHDL character types

Under ISE 7.1, I did a simple UART module that has a "terminating character" generic, which is of type character. (When...
1 comments posted 19yrs
posted by google
1 comments posted 19yrs posted by google

Xilin X-Fest Lunacy

I just got an invitation to this years SIlica/Xilinx X-fest. I've been to these before and found them useful so I was r...
18 comments posted 19yrs
posted by nospam
18 comments posted 19yrs posted by nospam

RLOC not working correctly in ISE 8.2 and 9.1?

I've been wondering if someone else has noticed that RLOCs does not seem to be working very well in ISE 8.2 and 9.1? Cu...
2 comments posted 19yrs
posted by ehliar
2 comments posted 19yrs posted by ehliar

data2mem crash

Hi everyone, I just installed a new workstation, a Core2 duro running linux 64 bits. But I can use data2bram on it, it...
1 comments posted 19yrs
posted by tnt-at-246tNt-dot-com
1 comments posted 19yrs posted by tnt-at-246tNt-dot-com