Xilinx Spartan DCM jitter spectrum

Hello all, Does anyone has some numbers on the frequency spectrum of the jitter from a DCM? The datasheet says the DCM has a jitter of 100ps but I would like to know a bit more about the spectrum to determine whether or not the clock from a DCM is usefull for sampling.

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Nico Coesel
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The power spectral density (the spectrum you would see on a spectrum analyzer) is extremely close to the carrier -- that is no spurs.

The reason for this is that if you make small adjustments to the delay lines every so many clocks, these small steps (~25ps steps) represent a tiny increase or decrease in the period of the clock, which means that there is a correspondingly tiny step of frequency that lasts for one period, and then is gone.

The result is gaussian noise bump in spectra around the carrier.

There are no other frequency components (unless they are already present in the input clock, in which case they come directly through -- a DCM does not attenuate jitter).

In the time domain, if you do a histogram of periods, you will get two overlapping (or more) gaussian distributions of period length: period - tap, period + tap, possible period + two taps, possible period - 2 taps. The time domain is the superposition of period lengths with and without the taps inserted. Since the change in tap is completely random (like flipping a coin each time), there is no determinism, and hence no rate at which changes occur, and no sub-harmonics, or sidebands.


Reply to
Austin Lesea

As i wanted to use a Spartan DCM i was also a bit sceptic how the Spectral Quality of it's generated clocks would be. First thing i did was Measure it with LeCroy Jitter Analysis. I did a JitterPeriod (which measures all the period's for one shot) followed by a FFT of these periods. I could not observe any significant spectral spikes this way other than what was caused by other things (power supply, crosstalk inside the logic, etc). The spectral quality was good.

But the bad thing about the DCM is it's "digital" behaviour compared to a classic PLL. Everything is fine as long as you supply a near ideal Clock to it's input. If you don't, you are lost. You can't use it as a jitter filter or as a clock recovery as you could with a classic PLL. And you have to be very careful and do extra effort in you design when there is a possibility the clock to a DCM can be disturbed (ESD, EMC).

I found out that there was no

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