I've been wondering if someone else has noticed that RLOCs does not seem to be working very well in ISE 8.2 and 9.1?
Currently I'm experimenting with a project where the RLOCs are working ok for smaller submodules but when I try to instantiate these submodules into a larger design in several places the RLOCs are lost in some way.
In ISE 8.1 everything is working as expected though.
/Andreas
My guess is you have an RPM that straddles a DSP or BRAM column. There is a bug in the mapper that has been there since 6.3 that messes up the grid mapping when an RPM has elements on both sides of a non-LUT column. The result is if you have a RAM16, SRL16 or other element that requires a LUT memory resource and it is placed on the opposite side of a BRAM or DSP column relative to the RLOC origin, it will fail to place. I think it may have gotten even more broken in 8.2 so that purely LUT RPMs also can't straddle a non-LUT resource.
I don't think this is the case because my design is placed correctly if I synthesize the design with XST 8.1 and place and route it using
8.2 or 9.1. (I did run into the problem you described a couple of months ago and a posting by you helped me solve that one.)I got some help from Xilinx on this issue and I might have to work around the problem by using constraints in the UCF file instead. It might also be that I am doing something weird in my code :)
All in all, I think that RLOCs might be more work than they are worth in my case but it has been interesting to learn a bit more about them and get some feeling for when they might be useful.
One experince I have had is that once you start to RLOC a module you really need to RLOC the modules that are closely connected to it as well, otherwise you will probably get suboptimal timing as compared to just letting par place everything automatically.
/Andreas
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