Field-Programmable Gate Arrays

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Xilinx SRL's and sync flip flops

I looked at Xilinx' sysnthesis template for double-registering asynchronous signals to avoid metastability problems. Th...
1 comments posted 19yrs
posted by mottoblatto
1 comments posted 19yrs posted by mottoblatto

sum of array

hi every body , please please how to calculate the sum of an array ( for example an array of std_logic_vector(3 downto 0...
14 comments posted 19yrs
posted by abaidik
14 comments posted 19yrs posted by abaidik

Modelsim - SDF incompatibility

Hi, I am using Modelsim to simulate placed-and-routed Xilinx design. I have noticed that in some cases iopath from sdf...
1 comments posted 19yrs
posted by ruzica
1 comments posted 19yrs posted by ruzica

faq

hi,this is balaji .I am doing my final year project using kcpsm3 (picoblaze).Any one sugg. any application using this co...
1 comments posted 19yrs
posted by 4balaji
1 comments posted 19yrs posted by 4balaji

3.3V tolerant Virtex-4 JTAG Configuration

Hello, I've been looking through Xilinx's website for quite some time now for information on using 3.3V to configure a...
2 comments posted 19yrs
posted by dale.prather
2 comments posted 19yrs posted by dale.prather

Heatsink on FPGA?

Hi, Anybody has experience with heatsinks on FPGAs? In the V5 documentation, Xilinx says the heatsink can be glued to t...
9 comments posted 19yrs
posted by jean-baptiste.nouvel
9 comments posted 19yrs posted by jean-baptiste.nouvel

/* synopsys enum state_code */ on XST???

The /*synopsys enum state_code*/ constraint is pretty handy to handle the FSM state encoding. Unfortunately XST doesn't...
1 comments posted 19yrs
posted by jean-baptiste.nouvel
1 comments posted 19yrs posted by jean-baptiste.nouvel

PAL

Hi, I'm working on colorbar generator VHDL code from Xilinx (file name cb_eg1.vhd, from Xapp514, Chapter 16). The forma...
1 comments posted 19yrs
posted by p.soegaard
1 comments posted 19yrs posted by p.soegaard

Initialization of arrays in Verilog

Hi! Can anybody give me a hint on how to initialize an array of registers in Verilog with Xilinx ISE 7.1i? I tried the...
3 comments posted 19yrs
posted by till
3 comments posted 19yrs posted by till

ISE synthesis works, XPS does not resolve symbol?

Hi all, I have a peripheral written in verlog, this is getting synthesized by ISE but then when I generate netlist usin...
1 comments posted 19yrs
posted by vbhanu
1 comments posted 19yrs posted by vbhanu

EDK & custom board definitions

Hi All, In the process of creating a custom board definition file for a new board I've developed I've discovered a few...
2 comments posted 19yrs
posted by ajg112
2 comments posted 19yrs posted by ajg112