Latest threads in Field-Programmable Gate Arrays

using system ACE for generic app data storage - file system intelligence required?

I have a V4FX12 application that could potentially benefit from having Gbytes of ROM data storage easily changeable thr...

1 19yrs

jcc

1 19yrs jcc

WTF? - Spartan-3E starter kit with no printed board manual?

Hi i'm outraged! Those guys from the X* company STOPPED DELIVERING printed manuals with their boards!!!! This is not ri...

8 19yrs

nkavv

8 19yrs nkavv

Xilinx SRL's and sync flip flops

I looked at Xilinx' sysnthesis template for double-registering asynchronous signals to avoid metastability problems. Th...

1 19yrs

mottoblatto

1 19yrs mottoblatto

sum of array

hi every body , please please how to calculate the sum of an array ( for example an array of std_logic_vector(3 downto 0...

14 19yrs

abaidik

14 19yrs abaidik

Modelsim - SDF incompatibility

Hi, I am using Modelsim to simulate placed-and-routed Xilinx design. I have noticed that in some cases iopath from sdf...

1 19yrs

ruzica

1 19yrs ruzica

Can you change the default settings for XST when running platgen?

Hi All, I have a design based around a PPC. The problem I have is that I would like to change the default setting for X...

0 19yrs

dontreplytothisaddy

0 19yrs dontreplytothisaddy

help !something wrong with Adaptive Filter (vhdl code)

3 parts partial products multiplier tap;LMP Adaptive Filter;Direct form fir filter core but quartus report that: Error...

2 19yrs

kangwei365

2 19yrs kangwei365

faq

hi,this is balaji .I am doing my final year project using kcpsm3 (picoblaze).Any one sugg. any application using this co...

1 19yrs

4balaji

1 19yrs 4balaji

3.3V tolerant Virtex-4 JTAG Configuration

Hello, I've been looking through Xilinx's website for quite some time now for information on using 3.3V to configure a...

2 19yrs

dale.prather

2 19yrs dale.prather

Heatsink on FPGA?

Hi, Anybody has experience with heatsinks on FPGAs? In the V5 documentation, Xilinx says the heatsink can be glued to t...

9 19yrs

jean-baptiste.nouvel

9 19yrs jean-baptiste.nouvel

/* synopsys enum state_code */ on XST???

The /*synopsys enum state_code*/ constraint is pretty handy to handle the FSM state encoding. Unfortunately XST doesn't...

1 19yrs

jean-baptiste.nouvel

1 19yrs jean-baptiste.nouvel

PAL

Hi, I'm working on colorbar generator VHDL code from Xilinx (file name cb_eg1.vhd, from Xapp514, Chapter 16). The forma...

1 19yrs

p.soegaard

1 19yrs p.soegaard

Initialization of arrays in Verilog

Hi! Can anybody give me a hint on how to initialize an array of registers in Verilog with Xilinx ISE 7.1i? I tried the...

3 19yrs

till

3 19yrs till

ISE synthesis works, XPS does not resolve symbol?

Hi all, I have a peripheral written in verlog, this is getting synthesized by ISE but then when I generate netlist usin...

1 19yrs

vbhanu

1 19yrs vbhanu

Estimating number of FPGAs needed for an application

Hi all I'm absolutely new to FPGAs, in fact my work is much more related with the SW than with the HW, so I need to sol...

6 19yrs

rbblasco

6 19yrs rbblasco

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