Latest threads in Field-Programmable Gate Arrays

RLOC not working correctly in ISE 8.2 and 9.1?

I've been wondering if someone else has noticed that RLOCs does not seem to be working very well in ISE 8.2 and 9.1? Cu...

2 19yrs

ehliar

2 19yrs ehliar

data2mem crash

Hi everyone, I just installed a new workstation, a Core2 duro running linux 64 bits. But I can use data2bram on it, it...

1 19yrs

tnt-at-246tNt-dot-com

1 19yrs tnt-at-246tNt-dot-com

Xilinx Spartan DCM jitter spectrum

Hello all, Does anyone has some numbers on the frequency spectrum of the jitter from a DCM? The datasheet says the DCM...

2 19yrs

nico

2 19yrs nico

Load V4 bitstream encryption key with XSVF

Hi. I want to load the bitstream encryption key on a V4FX board. Using IMPACT and a Xilinx download cable, I can succes...

2 19yrs

jetmarc

2 19yrs jetmarc

Driving PLL from general I/O in Altera Cyclone

I am trying to deserialize a DDR signal in my Cyclone. For reasons I won't go into the DDR clock comes in off a general...

9 19yrs

lloyd.rochester

9 19yrs lloyd.rochester

XILINX ISE PAR error: CLK0_BUFG_INST is not placed

Dear all, while performing a Place and Route of a reconfigurable project (developed followinf the Early Access User Gui...

0 19yrs

lucaroccasalva

0 19yrs lucaroccasalva

Xilinx CoreGen fifo - ngdbuild error

Hi everybody, since one day I am fighting with a Xilinx CoreGen IP. I am using Mentor Graphics Precision 2006a.101 and...

3 19yrs

fras

3 19yrs fras

How best do I implement routing boxes in RTL?

In the design I have 256 3-bit registers, every time I need to read or write 16 of them (data_o0, 1, ...15). The read/w...

3 19yrs

newsreader

3 19yrs newsreader

CAN vhdl code document

hi, i have downloaded the CAN VHDL from opencores but am unable to understand the code. can anyone please tell me where...

1 19yrs

barukula.ramesh

1 19yrs barukula.ramesh

odd warning in Xilinx ISE webpack

At the XST-synthesize stage, I'm getting this weird warning: "Property use_dsp48" is not applicable for this technology...

7 19yrs

thesteveman_ice9

7 19yrs thesteveman_ice9

Avnet Virtex-4 FX12 mini module

Hello, I have recently bought Avnet Virtex-4 FX12 mini module. I am trying to implement the Gigabit ethernet communicat...

5 19yrs

jrabbani

5 19yrs jrabbani

FPGA Vs ASIC design and implementation

Hi, Being familiar with FPGA design and implementation flow and illiterate with ASIC corresponding one. My question is...

5 19yrs

karl.polytech

5 19yrs karl.polytech

using XIlinx impact in batch mode to generate EEPROM files

I am using xilinx tools in an unix system to do the P&R and generate the bit file. I am using a batch mode script to go...

4 19yrs

dipumisc

4 19yrs dipumisc

Introducing picosecond delay between two output signals

Hi, I would like to know what are the common methods of introducing delays as low as 10ps between two outputs in an FPG...

15 19yrs

axr0284

15 19yrs axr0284

DFF with clock and async-preset tied together

Assume we have this VHDL model process(sig) begin if ( sig = '1' ) then q

1 19yrs

ccon67

1 19yrs ccon67

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