Field-Programmable Gate Arrays

Xilinx Spartan DCM jitter spectrum

Hello all, Does anyone has some numbers on the frequency spectrum of the jitter from a DCM? The datasheet says the DCM...

2 comments posted 19yrs

posted by nico

2 comments posted 19yrs posted by nico

Load V4 bitstream encryption key with XSVF

Hi. I want to load the bitstream encryption key on a V4FX board. Using IMPACT and a Xilinx download cable, I can succes...

2 comments posted 19yrs

posted by jetmarc

2 comments posted 19yrs posted by jetmarc

Driving PLL from general I/O in Altera Cyclone

I am trying to deserialize a DDR signal in my Cyclone. For reasons I won't go into the DDR clock comes in off a general...

9 comments posted 19yrs

posted by lloyd.rochester

9 comments posted 19yrs posted by lloyd.rochester

XILINX ISE PAR error: CLK0_BUFG_INST is not placed

Dear all, while performing a Place and Route of a reconfigurable project (developed followinf the Early Access User Gui...

0 comments posted 19yrs

posted by lucaroccasalva

0 comments posted 19yrs posted by lucaroccasalva

Xilinx CoreGen fifo - ngdbuild error

Hi everybody, since one day I am fighting with a Xilinx CoreGen IP. I am using Mentor Graphics Precision 2006a.101 and...

3 comments posted 19yrs

posted by fras

3 comments posted 19yrs posted by fras

How best do I implement routing boxes in RTL?

In the design I have 256 3-bit registers, every time I need to read or write 16 of them (data_o0, 1, ...15). The read/w...

3 comments posted 19yrs

posted by newsreader

3 comments posted 19yrs posted by newsreader

CAN vhdl code document

hi, i have downloaded the CAN VHDL from opencores but am unable to understand the code. can anyone please tell me where...

1 comments posted 19yrs

posted by barukula.ramesh

1 comments posted 19yrs posted by barukula.ramesh

odd warning in Xilinx ISE webpack

At the XST-synthesize stage, I'm getting this weird warning: "Property use_dsp48" is not applicable for this technology...

7 comments posted 19yrs

posted by thesteveman_ice9

7 comments posted 19yrs posted by thesteveman_ice9

Avnet Virtex-4 FX12 mini module

Hello, I have recently bought Avnet Virtex-4 FX12 mini module. I am trying to implement the Gigabit ethernet communicat...

5 comments posted 19yrs

posted by jrabbani

5 comments posted 19yrs posted by jrabbani

FPGA Vs ASIC design and implementation

Hi, Being familiar with FPGA design and implementation flow and illiterate with ASIC corresponding one. My question is...

5 comments posted 19yrs

posted by karl.polytech

5 comments posted 19yrs posted by karl.polytech

using XIlinx impact in batch mode to generate EEPROM files

I am using xilinx tools in an unix system to do the P&R and generate the bit file. I am using a batch mode script to go...

4 comments posted 19yrs

posted by dipumisc

4 comments posted 19yrs posted by dipumisc

Introducing picosecond delay between two output signals

Hi, I would like to know what are the common methods of introducing delays as low as 10ps between two outputs in an FPG...

15 comments posted 19yrs

posted by axr0284

15 comments posted 19yrs posted by axr0284

DFF with clock and async-preset tied together

Assume we have this VHDL model process(sig) begin if ( sig = '1' ) then q

1 comments posted 19yrs

posted by ccon67

1 comments posted 19yrs posted by ccon67

Spartan3AN - Roadmap

Hi, I just got a newsletter stating the Spartan3AN being available now. While these Spartan3AN are market as "new non-v...

22 comments posted 19yrs

posted by carlhermann.schlehaus

22 comments posted 19yrs posted by carlhermann.schlehaus

DCI termination mismatch error reported in ise91

Hi : i am using ise 9.1i to run my designs which containted lvds . In my ucf file , there are constrains like NET "Ring...

0 comments posted 19yrs

posted by black.huang

0 comments posted 19yrs posted by black.huang