Field-Programmable Gate Arrays

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Xilinx Synthesis Attribute usage

Xilinx gurus out there, I have a very very simple design with a 24 bit counter, and I am using bit 24 in an always bloc...
6 comments posted 19yrs
posted by jceven
6 comments posted 19yrs posted by jceven

chipscope

Hi, i have used a parallel cable to download bitfile into my Virtex 4 FPGA. But when open Chipscope with this cable, th...
1 comments posted 19yrs
posted by chenyong20000
1 comments posted 19yrs posted by chenyong20000

init of FPGA's Block-RAMs.

Bonjour, My name is Julien Lochen, I work as FPGA Design Engineer in France. My question is about the init of FPGA's RA...
2 comments posted 19yrs
posted by lochen
2 comments posted 19yrs posted by lochen

How to generate sgmii interface?

I want to generate sgmii interface with coregen. I choose this IP-"Ethernet 1000BASE-X PCS/PMA or SGMII" , when i gener...
2 comments posted 19yrs
posted by mynewlifever
2 comments posted 19yrs posted by mynewlifever

old Quartus project files

I have to work again on an old project started 2004 with Quartus v3.0. Now I'm working with the actual v6.1. There are...
1 comments posted 19yrs
posted by manfred.balik
1 comments posted 19yrs posted by manfred.balik

Problem with XESS XSA 3S1000!

I have created a simple project using Microblaze v4.0a and I use XESS XSA 3S1000,XStend v3.0 board. The project only ha...
0 comments posted 19yrs
posted by tranxuantoan
0 comments posted 19yrs posted by tranxuantoan

How to use the DDR SDRAM instead of Block RAM?

Hi, I have a design that is implemented on the Virtex4 and it consumes 69 FIFO16/RAMB16s. I hope to be able to implemen...
10 comments posted 19yrs
posted by csoon
10 comments posted 19yrs posted by csoon

DCM Autoconfiguration??

I have ported a project that was developed on an ML401 Virtex4 board over to an Avnet Virtex4 PCI-E board. The ML401 us...
4 comments posted 19yrs
posted by mottoblatto
4 comments posted 19yrs posted by mottoblatto

XIlinx 9.2 'partition' mode problem - s/w dies....

I've tired using the Xilinx 'partition' feature several times now with very mixed/negative results. I tried partions ag...
1 comments posted 19yrs
posted by johnp3+nospam
1 comments posted 19yrs posted by johnp3+nospam

ChipScope problem: "Waiting for core to be armed".

Hi, All The ChipScope gave me the message "Waiting for core to be armed" while the program can run on the board at the...
7 comments posted 19yrs
posted by pang.dudu.pang
7 comments posted 19yrs posted by pang.dudu.pang

Fpga sdr boards / kits

Need to find a decent fpga sdr board or kit - preferably xilinx. Trying to buy a premade kit rather than assembling our...
0 comments posted 19yrs
posted by news
0 comments posted 19yrs posted by news

Xilinx Xplorer misfunction

Hello, I would like to know if anyone experiences this misfunction in Xplorer tool. I'm using Xilinx ISE 8.2i. When I u...
1 comments posted 19yrs
posted by maybetooparanoid
1 comments posted 19yrs posted by maybetooparanoid

doubt in verilog coding

hai, i am vishnu i have some doubt regarding verilog coding,i want to have 5 secs delay ,as delays are not synthesziabl...
5 comments posted 19yrs
posted by ravipativishnu
5 comments posted 19yrs posted by ravipativishnu