Latest threads in Field-Programmable Gate Arrays

Xilinx ISE support for dual/quad core CPUs?

Hi, I'm about to buy a new workstation for FPGA development and I'm hesitating between a Core 2 Extreme @ 2.93 GHz (X68...

16 19yrs

prdubois

16 19yrs prdubois

Virtex5 LXT and synthesis..

Folks, I need to do a trial synthesis to see if one of our ASIC design module will run at speed (~312.5Mhz) in Xilinx V...

4 19yrs

cshroff

4 19yrs cshroff

Xilinx Synthesis Attribute usage

Xilinx gurus out there, I have a very very simple design with a 24 bit counter, and I am using bit 24 in an always bloc...

6 19yrs

jceven

6 19yrs jceven

XILINX ISE: How to define a Internal clock and use it in OFFSET command?

Hi, I have a input clock "i_clk_main", in my VHDL code, i divide this clk with factor 2, that means "clk_int" has the h...

1 19yrs

uvbaz

1 19yrs uvbaz

chipscope

Hi, i have used a parallel cable to download bitfile into my Virtex 4 FPGA. But when open Chipscope with this cable, th...

1 19yrs

chenyong20000

1 19yrs chenyong20000

init of FPGA's Block-RAMs.

Bonjour, My name is Julien Lochen, I work as FPGA Design Engineer in France. My question is about the init of FPGA's RA...

2 19yrs

lochen

2 19yrs lochen

How to generate sgmii interface?

I want to generate sgmii interface with coregen. I choose this IP-"Ethernet 1000BASE-X PCS/PMA or SGMII" , when i gener...

2 19yrs

mynewlifever

2 19yrs mynewlifever

old Quartus project files

I have to work again on an old project started 2004 with Quartus v3.0. Now I'm working with the actual v6.1. There are...

1 19yrs

manfred.balik

1 19yrs manfred.balik

Problem with XESS XSA 3S1000!

I have created a simple project using Microblaze v4.0a and I use XESS XSA 3S1000,XStend v3.0 board. The project only ha...

0 19yrs

tranxuantoan

0 19yrs tranxuantoan

How to use the DDR SDRAM instead of Block RAM?

Hi, I have a design that is implemented on the Virtex4 and it consumes 69 FIFO16/RAMB16s. I hope to be able to implemen...

10 19yrs

csoon

10 19yrs csoon

DCM Autoconfiguration??

I have ported a project that was developed on an ML401 Virtex4 board over to an Avnet Virtex4 PCI-E board. The ML401 us...

4 19yrs

mottoblatto

4 19yrs mottoblatto

XIlinx 9.2 'partition' mode problem - s/w dies....

I've tired using the Xilinx 'partition' feature several times now with very mixed/negative results. I tried partions ag...

1 19yrs

johnp3+nospam

1 19yrs johnp3+nospam

ChipScope problem: "Waiting for core to be armed".

Hi, All The ChipScope gave me the message "Waiting for core to be armed" while the program can run on the board at the...

7 19yrs

pang.dudu.pang

7 19yrs pang.dudu.pang

Verilog DSP Examples (FFT With 32K-Point Transform Length, FIR, IIR, Discrete Cosine Transform (DCT), Convolution 2D)

Hi, Here there are some examples in Verilog of functions DSP for FPGAs, some of these are: http://www.altera.com/suppor...

0 19yrs

jrquevedor

0 19yrs jrquevedor

Fpga sdr boards / kits

Need to find a decent fpga sdr board or kit - preferably xilinx. Trying to buy a premade kit rather than assembling our...

0 19yrs

news

0 19yrs news

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