How to generate sgmii interface?

I want to generate sgmii interface with coregen. I choose this IP-"Ethernet 1000BASE-X PCS/PMA or SGMII" , when i generate, I never find sgmii interface except sgmii_clk signal. So i want to ask where is the serial data bus?

Thank you!

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Do you want to have conenction EMAC-SGMII-ext. Phy? Then its best to use CoreGen TemacWrapper v4.3/v4.3. You'll get a complete design here.

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It is unclear on what device you are targeting, but it is very easy to use CoreGen to generate an example design for 1000-BaseX (assuming you are using the embedded EMAC block). It is a simple loopback for non-jumbo sized frames.

Before we released Virtex-5, I tested the example design on our ML525 RocketIO Characterization board and can confirm it does work for SGMII

1000Base-X modes. As a matter fo fact, the CoreGen example was used in part of the design that we took to UNH for compliance testing (and passed with it). The only modification required is the addition of a .UCF file.

If using Virtex-5, you will need the to have the (9.1i) CoreGen IP update installed to see the 'Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper' core visible. What core are you using and what device are you targeting?


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