Field-Programmable Gate Arrays

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Xilinx Xplorer misfunction

Hello, I would like to know if anyone experiences this misfunction in Xplorer tool. I'm using Xilinx ISE 8.2i. When I u...
1 comments posted 19yrs
posted by maybetooparanoid
1 comments posted 19yrs posted by maybetooparanoid

doubt in verilog coding

hai, i am vishnu i have some doubt regarding verilog coding,i want to have 5 secs delay ,as delays are not synthesziabl...
5 comments posted 19yrs
posted by ravipativishnu
5 comments posted 19yrs posted by ravipativishnu

.bit file to VHDL/verilog source code

I am currently working on an old board which have eight FPGA XC3130 on board and i dont have a source code for those FP...
8 comments posted 19yrs
posted by lingamaneni.naveen
8 comments posted 19yrs posted by lingamaneni.naveen

Welcome to X-Fest 2007

Now that all silly disclaimers have been thoroughly eradicated, come and sign up for X-Fest in a city near you. Whether...
0 comments posted 19yrs
posted by alfke
0 comments posted 19yrs posted by alfke

SEC:U Problem getting rid of bit latch errors

How do I get rid of bit latch type warnings compiling with Xilinx ISE when I am assigning a value to part of a bit vect...
4 comments posted 19yrs
posted by maurizio.gencarelli
4 comments posted 19yrs posted by maurizio.gencarelli

Clearing fpga internal memory...

Hi, I have set of registers implemented as internal RAM blocks (in Cyclone FPGA). Is there any way to clear contents of...
12 comments posted 19yrs
posted by yrjola
12 comments posted 19yrs posted by yrjola

Xilinx Netlist

Is there an easy way to get the Xilinx design manager to spit out a netlist for a synthesized VHDL file? Adam
10 comments posted 19yrs
posted by aelbirt
10 comments posted 19yrs posted by aelbirt

Xilinx FPGA, OFFSET OUT AFTER

hi, I want to operate the XILINX Virtex-4 XC4VLX60(Speed -12) at a frequenz of 130 MHz. So i write the following constr...
6 comments posted 19yrs
posted by uvbaz
6 comments posted 19yrs posted by uvbaz

interface ad9229 with altera stratix II

can some one give me a hint on how to interface AD9229 a to d converter with stratix II lvds interface? the AD9229 outp...
1 comments posted 19yrs
posted by yanwain
1 comments posted 19yrs posted by yanwain

Programming XCF from MicroBlaze over JTAG???

Hi, Has anyone had any success in programming a Xilinx XCF using C code in a MicroBlaze over the JTAG ports? Any informa...
25 comments posted 19yrs
posted by bgolinda
25 comments posted 19yrs posted by bgolinda

ANNC: Clock Network Implementation Webcast

Lattice is holding a webcast tomorrow Wednesday, March 14, "Revolutionizing Clock Network Implementation." The presente...
0 comments posted 19yrs
posted by bart.borosky
0 comments posted 19yrs posted by bart.borosky

PCI - Express

My understanding of the initialising sequence for a PCI-E card is as follows: 1 Detect phase to see if there's a receiv...
1 comments posted 19yrs
posted by Tim
1 comments posted 19yrs posted by Tim