Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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using system ACE for generic app data storage - file system intelligence required?
I have a V4FX12 application that could potentially benefit from having Gbytes of ROM data storage easily changeable through a CF card, so the system ACE CF thing looks sort of interesting. We are...
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17 years ago
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WTF? - Spartan-3E starter kit with no printed board manual?
Hi i'm outraged! Those guys from the X* company STOPPED DELIVERING printed manuals with their boards!!!! This is not right. For $149 plus international shipping rates, I demand a printed manual as...
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17 years ago
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Xilinx SRL's and sync flip flops
I looked at Xilinx' sysnthesis template for double-registering asynchronous signals to avoid metastability problems. They explicitly state that an SRL primitive should NOT be extracted. Why is this? I...
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17 years ago
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sum of array
hi every body , please please how to calculate the sum of an array ( for example an array of std_logic_vector(3 downto 0) ) thank you
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17 years ago
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Modelsim - SDF incompatibility
Hi, I am using Modelsim to simulate placed-and-routed Xilinx design. I have noticed that in some cases iopath from sdf is being treated as a transport delay and in some other as inertial delay,...
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17 years ago
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Can you change the default settings for XST when running platgen?
Hi All, I have a design based around a PPC. The problem I have is that I would like to change the default setting for XST when running platgen. Platgen will generate a default synthesis project file...
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17 years ago
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help !something wrong with Adaptive Filter (vhdl code)
3 parts partial products multiplier tap;LMP Adaptive Filter;Direct form fir filter core but quartus report that: Error (10334): VHDL error at tap.vhd(82): entity "tsb" is used but not declared 2...
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17 years ago
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faq
hi,this is balaji .I am doing my final year project using kcpsm3 (picoblaze).Any one sugg. any application using this core.Which i can complete in around 20 days. thank u ,for responding
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17 years ago
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3.3V tolerant Virtex-4 JTAG Configuration
Hello, I've been looking through Xilinx's website for quite some time now for information on using 3.3V to configure a Virtex-4 through the JTAG interface. Is there anything equivalent to the link...
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17 years ago
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Heatsink on FPGA?
Hi, Anybody has experience with heatsinks on FPGAs? In the V5 documentation, Xilinx says the heatsink can be glued to the FPGA but that it is safer to screw it to the board to avoid mechanical...
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17 years ago
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/* synopsys enum state_code */ on XST???
The /*synopsys enum state_code*/ constraint is pretty handy to handle the FSM state encoding. Unfortunately XST doesn't seem to be managing it correctly (as opposed to other synthesisers). Not...
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17 years ago
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PAL
Hi, I'm working on colorbar generator VHDL code from Xilinx (file name cb_eg1.vhd, from Xapp514, Chapter 16). The format is NTSC. Is there anyone who has modified the code to PAL format? I've inserted...
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17 years ago
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Initialization of arrays in Verilog
Hi! Can anybody give me a hint on how to initialize an array of registers in Verilog with Xilinx ISE 7.1i? I tried the following code: | reg [9:0] palette [3:0]; | // synthesis attribute INIT of...
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17 years ago
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ISE synthesis works, XPS does not resolve symbol?
Hi all, I have a peripheral written in verlog, this is getting synthesized by ISE but then when I generate netlist using XPS it fails to resolve a function symbol. Could someone please explain what...
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17 years ago
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Estimating number of FPGAs needed for an application
Hi all I'm absolutely new to FPGAs, in fact my work is much more related with the SW than with the HW, so I need to solve a problem that ideally I was not targeted to. The issue is this: I have to...
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17 years ago
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