I have ported a project that was developed on an ML401 Virtex4 board over to an Avnet Virtex4 PCI-E board. The ML401 uses a V4LX25 and the Avnet board uses a V4FX60. The only changes I made to the project had to do with just reassigning signals in the UCF.
I have 2 DCM's in the project. Each DCM's lock signal is routed out to an LED on the board. Each DCM's output clock is routed to a header pin (as well as elsewhere in the design). After configuration (or after a pushbutton RESET to the FPGA) the lock LED's light and the output clocks are valid. This lasts about half a second. Then everything goes dead. So lock is high and valid clocks are output for at least hundreds of thousands of cycles. Then nothing. I can press the RESET button (resets the DCM's -- their lock's are used to distribute sync resets to the rest of the logic in the design) and the lock LED's light and the clocks are valid -- again, only for about half a second.
One difference I noticed is that the ISE reports that the DCM hierarchical names have changed due to DCM Autocalibration. There are also multiple refences to this DCM autocalibration in various reports. I have never heard of this, and I can't find info on Xilinx site. Is there something different that happens with DCM's on V4FX parts compared to V4LX parts? I have checked Avnet app notes on this board. Their UCF doesn't have anything special in it that I overlooked.
This is a weird problem I haven't looked in to very hard. Thought I would ask here to see if it is a bonehead move on my part : )
Thanks!