Latest threads in Field-Programmable Gate Arrays

Issues with the BBD file, using a core generated using ISE coregenerator

Hi all, I have a few issues with how to use the BBD file. key words ISE 8.2, XPS 8.2, BBD file, CORE Generator step1. I...

1 19yrs

narashimanc

1 19yrs narashimanc

There is something (other) like his?

http://www.seventech.it/english/prodotti.php Jamma platform for gaming with SDK Thanx

0 19yrs

nomail

0 19yrs nomail

Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.

Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals. We need t...

13 19yrs

Xieyu1219

13 19yrs Xieyu1219

Compiling a library

Hello, I am trying to simulate a VHDL code (using ISE 9) and I am getting the following error: ERROR:Simulator:235 - Pa...

3 19yrs

(myname_here)_123456

3 19yrs (myname_here)_123456

Printing problem with Ise 9.1.03i

Hi all, I'm using Ise 9.1.03i. when I try to print a code written in Ise text editor, I get this error: "Print fails be...

7 19yrs

mazouz.nezhate

7 19yrs mazouz.nezhate

ISE Smart Ident

Hello, Is there any facility in ISE to automatically indent source code? The similar technique is available in C/C++ ed...

2 19yrs

(myname_here)_123456

2 19yrs (myname_here)_123456

BFM simulation and number of Masters?

Hello, First of all I will make my question: Could you please say me how many Masters can be connected to the Bus when...

1 19yrs

le_marq

1 19yrs le_marq

Analog FPGAs: how fast?

What sorts of frequencies can currently-available analog FPGAs run at? (Either pure analog, or mixed such as the Actel...

0 19yrs

dmpalmer

0 19yrs dmpalmer

ModelSim Waveform naming question

I am using ModelSim SE and was wondering if there is a way to make a waveform display mnemonics. I am simulating a stat...

7 19yrs

mottoblatto

7 19yrs mottoblatto

Any recommendations for FPGA PCI development board?

I want to buy a FPGA PCI development board supporting the following features: 1. Large FPGA device, Xilinx FPGA prefere...

2 19yrs

hitsx

2 19yrs hitsx

Block RAM strange behavior, address off by one

I am getting a strange error with Block RAM on a Spartan 3 FPGA. Every time I issue a read, the word at the location pr...

11 19yrs

mhs000

11 19yrs mhs000

creating library in ISE 9

Hello, I am newbie in VHDL. I want to create a library with several pkg on it so when I am creating a new library; I co...

2 19yrs

(myname_here)_123456

2 19yrs (myname_here)_123456

80000 Bit Shift Register

I am implementing an 80000 Element Shift register to be used as a very long (1Sec) digital delay generator. (Yes, its t...

14 19yrs

emh203

14 19yrs emh203

No Synplify evaluation?

Good afternoon.. Has anyone being lucky in the past getting a Synplify for Linux evaluation license? Mentor has some on...

1 19yrs

Richard Klingler

1 19yrs Richard Klingler

xilinx unused I/O state

Hi, What is the default state of the unused I/O pins for Xilinx FPGA (Spartan 3E)? For Altera FPGA, it can be set as in...

2 19yrs

eejju

2 19yrs eejju

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays