Field-Programmable Gate Arrays

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Compiling a library

Hello, I am trying to simulate a VHDL code (using ISE 9) and I am getting the following error: ERROR:Simulator:235 - Pa...
3 comments posted 19yrs
posted by (myname_here)_123456
3 comments posted 19yrs posted by (myname_here)_123456

Printing problem with Ise 9.1.03i

Hi all, I'm using Ise 9.1.03i. when I try to print a code written in Ise text editor, I get this error: "Print fails be...
7 comments posted 19yrs
posted by mazouz.nezhate
7 comments posted 19yrs posted by mazouz.nezhate

ISE Smart Ident

Hello, Is there any facility in ISE to automatically indent source code? The similar technique is available in C/C++ ed...
2 comments posted 19yrs
posted by (myname_here)_123456
2 comments posted 19yrs posted by (myname_here)_123456

BFM simulation and number of Masters?

Hello, First of all I will make my question: Could you please say me how many Masters can be connected to the Bus when...
1 comments posted 19yrs
posted by le_marq
1 comments posted 19yrs posted by le_marq

Analog FPGAs: how fast?

What sorts of frequencies can currently-available analog FPGAs run at? (Either pure analog, or mixed such as the Actel...
0 comments posted 19yrs
posted by dmpalmer
0 comments posted 19yrs posted by dmpalmer

ModelSim Waveform naming question

I am using ModelSim SE and was wondering if there is a way to make a waveform display mnemonics. I am simulating a stat...
7 comments posted 19yrs
posted by mottoblatto
7 comments posted 19yrs posted by mottoblatto

Block RAM strange behavior, address off by one

I am getting a strange error with Block RAM on a Spartan 3 FPGA. Every time I issue a read, the word at the location pr...
11 comments posted 19yrs
posted by mhs000
11 comments posted 19yrs posted by mhs000

creating library in ISE 9

Hello, I am newbie in VHDL. I want to create a library with several pkg on it so when I am creating a new library; I co...
2 comments posted 19yrs
posted by (myname_here)_123456
2 comments posted 19yrs posted by (myname_here)_123456

80000 Bit Shift Register

I am implementing an 80000 Element Shift register to be used as a very long (1Sec) digital delay generator. (Yes, its t...
14 comments posted 19yrs
posted by emh203
14 comments posted 19yrs posted by emh203

No Synplify evaluation?

Good afternoon.. Has anyone being lucky in the past getting a Synplify for Linux evaluation license? Mentor has some on...
1 comments posted 19yrs
posted by Richard Klingler
1 comments posted 19yrs posted by Richard Klingler

xilinx unused I/O state

Hi, What is the default state of the unused I/O pins for Xilinx FPGA (Spartan 3E)? For Altera FPGA, it can be set as in...
2 comments posted 19yrs
posted by eejju
2 comments posted 19yrs posted by eejju

define variable in ISE9.1 Tcl scripts

Hi, I've a question about ISE9.1 Tcl scripts. Is it possible to include `define in Tcl project scripts to determine mod...
1 comments posted 19yrs
posted by michel.talon
1 comments posted 19yrs posted by michel.talon

plb_tft_cntlr_ref for an ML405 EDK Project

Dear all, I am working with an ML405 and trying to put together a project of my own that uses the plb_tft_cntlr_ref IP...
6 comments posted 19yrs
posted by petermendham
6 comments posted 19yrs posted by petermendham