Hello, Is there any facility in ISE to automatically indent source code? The similar technique is available in C/C++ editors and I it is very simple to add it to ISE for indenting smartly VHDL and Verilog source codes.
Regards
mans schrieb:
Not as far as I know. But you can tell ISE to use an external editor like Xemcas, Notepad++, Eclipse with the VHDL-plugin... they all have indentation, syntax highlighting, templates, code folding...
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Wow, TWO votes for the ISE text editor ...
-a
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