Field-Programmable Gate Arrays

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Help: Best use of DCM in Spartan-3A?

For my design I must use two DCMs in series. How do I best use the CLKIN, RST, CLKFX and the LOCKED pin of the DCM? Sho...
5 comments posted 19yrs
posted by tool
5 comments posted 19yrs posted by tool

what is register packing?

I am reading Cyclone II device handbook. A concept, register packing confuses me. I know if we use the LUT and register...
2 comments posted 19yrs
posted by dechenxu
2 comments posted 19yrs posted by dechenxu

Inverse of a matrix

Hi all, Can anyone suggest simple algorithms for implementation of finding the inverse of a matrix (4 X 4)? Even inform...
4 comments posted 19yrs
posted by venkat.japan
4 comments posted 19yrs posted by venkat.japan

FIR Filter ON FPGA

Hi, I'm working on implementing an FIR Filter on a FPGA (Spartan 3E), here's what i want to accomplish --> The FIR Filt...
4 comments posted 19yrs
posted by bngguy
4 comments posted 19yrs posted by bngguy

Re: Docs on s/w interfacing EDK based design

> I am primarily interested in > s/w interfaces for accesing DDR memory like reading and writing data > at a particular...
0 comments posted 19yrs
posted by eric
0 comments posted 19yrs posted by eric

spartan-iie

I recently built a prototype using a xilinx spartan-iie specifically the xc2s150e-fgg456 which is programmed with an xc...
2 comments posted 19yrs
posted by jonpry
2 comments posted 19yrs posted by jonpry

Xilinx Seminars in Wiesbaden, Berlin, Hannover

X-Fest is a very successful and highly technical seminar series, given in 92 cities worldwide. For the June 5, 12, and...
18 comments posted 19yrs
posted by peter
18 comments posted 19yrs posted by peter

Xilinx Coregen 2.3 problem

Hi, We are using FIFO in our design. The FIFO has been generated using CoreGenerator 2.3. The programmable flags have b...
3 comments posted 19yrs
posted by vijayant.bhatnagar
3 comments posted 19yrs posted by vijayant.bhatnagar

Linux device driver for FPGA Xilinx Virtex-4

Hi, I'm finding a linux device driver for FPGA Xilinx Virtex-4, somebody can help me? thanks.
7 comments posted 19yrs
posted by greywolf82
7 comments posted 19yrs posted by greywolf82

Microchip ICD on FPGA

Hi, I want to implant a ICD into my Spartan 3 dev board. I need to program some Microchip PICs, and I wondered if I cou...
2 comments posted 19yrs
posted by fabien.goy
2 comments posted 19yrs posted by fabien.goy

How to calculate IFFT based on FFT result?

Dear All, I just wonder if there is a simple way to calculate IFFT based on FFT results? I was trying to configure xili...
2 comments posted 19yrs
posted by yao.sics
2 comments posted 19yrs posted by yao.sics

PacoBlaze 2.2

Dear group: PacoBlaze 2.2 has been released. This version solves some bugs that were still lurking in the stack and int...
5 comments posted 19yrs
posted by pablobleyer
5 comments posted 19yrs posted by pablobleyer

Quartus-II 7.1 Systemverilog interface?

I've tried using the "interface" construct in a Quartus-II project, but I can't tell if it's working the way it is supp...
3 comments posted 19yrs
posted by altera_user
3 comments posted 19yrs posted by altera_user