Field-Programmable Gate Arrays

Is this the correct way to design FPGA to DRAM interface?

Hi, there I am designing an FPGA to DRAM interface, which uses 160MHz clock. The clock cycle is 6ns, after gate level s...

0 comments posted 19yrs

posted by newsreader

0 comments posted 19yrs posted by newsreader

3rd Annual Opensource Telephony Developer Conference in Chicago, Illinois on June 26 to 28, 2007

3rd Annual Opensource Telephony Developer Conference in Chicago, Illinois on June 26 to 28, 2007 This is to invite your...

0 comments posted 19yrs

posted by nathanielanumba.gts

0 comments posted 19yrs posted by nathanielanumba.gts

Proper word for total delay?

What is the proper word that describes the total delay in a system from analog input to digital output (including phase...

1 comments posted 19yrs

posted by Slim

1 comments posted 19yrs posted by Slim

accesing JTAG ports on GPIOs

Hi there, I have a virtex II board (xc2v1000), unfortunately no jtag signals are routed on this board (TMS, TDI, TDO, T...

10 comments posted 19yrs

posted by sheikh.m.farhan

10 comments posted 19yrs posted by sheikh.m.farhan

Atmel FPSLIC users out there?

Hi, In the past I did some work with the Atmel FPSLIC. Eventually the project was changed and the FPSLIC was dropped. I...

3 comments posted 19yrs

posted by jetmarc

3 comments posted 19yrs posted by jetmarc

SignalTap Analyzer...

Hello, I created vhdl model of risc processor. During simulation it works correctly, but when I programmed and run it o...

2 comments posted 19yrs

posted by yrjola

2 comments posted 19yrs posted by yrjola

Quartus-II 7.1 Systemverilog support define `` ?

Does Quartus-II 7.1 support the Systemverilog preprocessor's `` concatenator? `define pori_reg(r) \ r

2 comments posted 19yrs

posted by xilinx_user

2 comments posted 19yrs posted by xilinx_user

Best way of moving paralell bits of data from over clock domains?

What is the best way to move paralell bits of data over two clock domains inside an xilinx FPGA (Spartan-3E) to avoid m...

2 comments posted 19yrs

posted by Daf

2 comments posted 19yrs posted by Daf

6502 FPGA core

I've implemented a first version of a 6502 core. It has a very simple architecture: First the command is read and then...

17 comments posted 19yrs

posted by fb

17 comments posted 19yrs posted by fb

Spartan3 LVCMOS33 Slew rate

I am using Spartan3 LVCMOS33 Open drain 24 mA output driver with 150 Ohm external pull-up to 1.8V. I would like to know...

32 comments posted 19yrs

posted by cpandya

32 comments posted 19yrs posted by cpandya

EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?

Hello all! Has anyone had success using LwIP along with some of the xilkernel functions in a system that is based on th...

8 comments posted 19yrs

posted by newsryan

8 comments posted 19yrs posted by newsryan

Interfacing EDK application code with Specific BRAMs on FPGA

Hello everybody, I m able to access/write DDR memory through a EDK application. I also want to interface with a ASIC on...

4 comments posted 19yrs

posted by koustav79

4 comments posted 19yrs posted by koustav79

PC to JTAG

I read all of the documents I could find about using the JTAG port as a communications interface to the FPGA and implem...

5 comments posted 19yrs

posted by mdhicks2

5 comments posted 19yrs posted by mdhicks2

low speed communication

Hi everybody, I have two Virtex4 FX12 Minimodules and I'd like to make them communicate eachother. These modules don't...

13 comments posted 19yrs

posted by cispa

13 comments posted 19yrs posted by cispa

IOSTANDARD user constrain

Hi, Is there a quick way to constraint all IO to the same standard? The default for Spartan3 is LVCMOS25 but we want th...

4 comments posted 19yrs

posted by ccon67

4 comments posted 19yrs posted by ccon67