Latest threads in Field-Programmable Gate Arrays

JTAG fundamentals question

Hi everyone, I tried to figure this one out myself but it turns out not so easy for someone with this lack of experienc...

1 19yrs

K.Pisaniec

1 19yrs K.Pisaniec

MPMC2 + flash bootloader problem

Hello, Does anyone else have problems with MPMC2 + flash bootloader in EDK v9? I started a design on the FX12 mini-modu...

2 19yrs

prdubois

2 19yrs prdubois

Is this the correct way to design FPGA to DRAM interface?

Hi, there I am designing an FPGA to DRAM interface, which uses 160MHz clock. The clock cycle is 6ns, after gate level s...

0 19yrs

newsreader

0 19yrs newsreader

3rd Annual Opensource Telephony Developer Conference in Chicago, Illinois on June 26 to 28, 2007

3rd Annual Opensource Telephony Developer Conference in Chicago, Illinois on June 26 to 28, 2007 This is to invite your...

0 19yrs

nathanielanumba.gts

0 19yrs nathanielanumba.gts

Proper word for total delay?

What is the proper word that describes the total delay in a system from analog input to digital output (including phase...

1 19yrs

Slim

1 19yrs Slim

accesing JTAG ports on GPIOs

Hi there, I have a virtex II board (xc2v1000), unfortunately no jtag signals are routed on this board (TMS, TDI, TDO, T...

10 19yrs

sheikh.m.farhan

10 19yrs sheikh.m.farhan

Atmel FPSLIC users out there?

Hi, In the past I did some work with the Atmel FPSLIC. Eventually the project was changed and the FPSLIC was dropped. I...

3 19yrs

jetmarc

3 19yrs jetmarc

SignalTap Analyzer...

Hello, I created vhdl model of risc processor. During simulation it works correctly, but when I programmed and run it o...

2 19yrs

yrjola

2 19yrs yrjola

Quartus-II 7.1 Systemverilog support define `` ?

Does Quartus-II 7.1 support the Systemverilog preprocessor's `` concatenator? `define pori_reg(r) \ r

2 19yrs

xilinx_user

2 19yrs xilinx_user

Best way of moving paralell bits of data from over clock domains?

What is the best way to move paralell bits of data over two clock domains inside an xilinx FPGA (Spartan-3E) to avoid m...

2 19yrs

Daf

2 19yrs Daf

6502 FPGA core

I've implemented a first version of a 6502 core. It has a very simple architecture: First the command is read and then...

17 19yrs

fb

17 19yrs fb

Spartan3 LVCMOS33 Slew rate

I am using Spartan3 LVCMOS33 Open drain 24 mA output driver with 150 Ohm external pull-up to 1.8V. I would like to know...

32 19yrs

cpandya

32 19yrs cpandya

EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?

Hello all! Has anyone had success using LwIP along with some of the xilkernel functions in a system that is based on th...

8 19yrs

newsryan

8 19yrs newsryan

Interfacing EDK application code with Specific BRAMs on FPGA

Hello everybody, I m able to access/write DDR memory through a EDK application. I also want to interface with a ASIC on...

4 19yrs

koustav79

4 19yrs koustav79

PC to JTAG

I read all of the documents I could find about using the JTAG port as a communications interface to the FPGA and implem...

5 19yrs

mdhicks2

5 19yrs mdhicks2

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