Hi, I'm working on implementing an FIR Filter on a FPGA (Spartan 3E), here's what i want to accomplish -->
The FIR Filter coefficients are generated on a host system using LabView, these coefficients are written to a RAM / PROM on a DSP card , the number of taps is constant but other parameters like sampling frequency and cut off frequencies can change according to requirements.
The FPGA reads these coefficients from the RAM / PROM and implements the FIR Filter.There should be a single bit file that is downloaded to configure the FPGA.
Any pointers in the right direction would be appreciated.
Thanks Tim