Quartus-II 7.1 Systemverilog interface?

Question

I've tried using the "interface" construct in a Quartus-II project, but I can't tell if it's working the way it is supposed to. I tried declaring an interface like the following:

interface interface_cpu_vgachar_vga( input logic [15:0] cpu_addr, input logic cpu_write, input logic cpu_read, input logic [15:0] cpu_wdata, output logic [15:0] cpu_rdata ); endinterface // : interface_cpu_vgachar_vga

interface interface_cpu_vgachar_cpu( output logic [15:0] cpu_addr, output logic cpu_write, output logic cpu_read, output logic [15:0] cpu_wdata, input logic [15:0] cpu_rdata ); endinterface // : interface_cpu_vgachar_cpu

When I use either interface as a top-level port, Altera's pin-assignment menu lists them as 'bidir'. And the synthesis-logfile shows a bunch of warnings like this: Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus if_cpu.cpu_rdata[0]~15 that it feeds Warning: The bidir "if_cpu.cpu_wdata[0]" has no source; inserted an always disabled tri-state buffer.

What am I doing wrong?

Edmond Coté · Accepted Answer

You are doing tons wrong ;)The interface specifies the collection of signals, and a modportdeclaration inside the interface specifies the direction of thosesignals, which is what I believe what you wanted to achieve.The following snippet should help you get started, but you'll find awealth of information online that can describe how to use interfacesmuch better than I ever could... in a short-time frame that is.interface cpu_if;  logic [15:0] cpu_addr;  logic          cpu_write;  logic          cpu_read;  logic [15:0] cpu_wdata;  logic [15:0] cpu_rdata;modport vga (  input  cpu_addr,  input  cpu_write,  input  cpu_read,  input  cpu_wdata,  output cpu_rdata);modport cpu (output cpu_addr,  output cpu_write,  output cpu_read,  output cpu_wdata,  input  cpu_rdata);endinterface // cpu_if-- Edmond Cot=E9

Altera User · Answer

Ok, I tried your suggestion, but Quartus-II doesn't seem to like interface-modports as port-declarations

module my_module( cpu_if.vga if_vga );

// ^^^ produces some arcane error about 'port direction' must be specified.

The error goes away if I drop the modport (.vga) from the port-declaration, but obviously, that just leads back to my original problem.

I'd be very grateful if you could post a known *working* example with modports in module-port declarations!

You are doing tons wrong ;)

The interface specifies the collection of signals, and a modport declaration inside the interface specifies the direction of those signals, which is what I believe what you wanted to achieve.

The following snippet should help you get started, but you'll find a wealth of information online that can describe how to use interfaces much better than I ever could... in a short-time frame that is.

interface cpu_if; logic [15:0] cpu_addr; logic cpu_write; logic cpu_read; logic [15:0] cpu_wdata; logic [15:0] cpu_rdata;

modport vga ( input cpu_addr, input cpu_write, input cpu_read, input cpu_wdata, output cpu_rdata );

modport cpu ( output cpu_addr, output cpu_write, output cpu_read, output cpu_wdata, input cpu_rdata );

endinterface // cpu_if

-- Edmond Coté

Edmond Coté · Answer

Last I checked it was supported.Take a look at the (older) LRM: -- Edmond Cot=E9

Quartus-II 7.1 Systemverilog interface?

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