Xilinx Coregen 2.3 problem

On May 29, 3:17 pm, Vijayant wrote: Hi, We are using FIFO in our design. The FIFO has been generated using CoreGenerator 2.3. The programmable flags have been enabled. The threshold values have been kept within the depth limit. However, when we try to synthesize on Xilinx, we get warnings: WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert' has no driver WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/ prog_empty_thresh_assert' has no driver

Similar warnings are got for 'prog_empty_thresh_assert', 'prog_full_thresh_negate', 'prog_full_thresh', 'prog_empty_thresh_negate', 'prog_empty_thresh',

Secondly, our top level entity of the FIFO generated by Coregen does not have signals labeled rd_clk and wr_clk. Still we got the following errors : NgdBuild:452 - logical net 'fifo1/fifo1/BU2/rd_clk' has no driver NgdBuild:452 - logical net 'fifo1/fifo1/BU2/wr_clk' has no driver

Pls help.

Regards, Vijayant

Hi Gurus, I need help desperately. Please help.

Regards, Vijayant

Can you find the instantiation of BU2 in your code? You'll need to have ports on BU2 of rd_clk, wr_clk, and prog_empty_thresh_assert. I can't comment on why this aren't connected in the coregen output according to your flow, only that there are ports (according to the software) and they don't appear to be connected (in BU2, according to the software).

Good luck on this very basic level of "looking at your code."