spartan-iie

The Program pin is active low, so pulling it high is the right thing to do.

Make sure you have all of the JTAG connections to the FPGA. A bad TMS connection for instance could cause the FPGA to enter a boudary scan test mode rather than program mode. This could also explain why you can't initialize the chain with the FPGA in place.

Also check all of the power supplies to the FPGA. You need core power and also Vcco for the appropriate banks. Look at the data sheet to see which supply runs the TDO pin.

And double check the PROG_B pin connection to be sure it is on the CF output of the prom. Make sure the mode pins of the FPGA are set for master serial or JTAG mode (master serial if you want it to boot up from the PROM, JTAG mode really just disables other modes so you can debug the JTAG problem easier).

HTH, Gabor

It is hard to tell if things are connected to the bga. I'm thinking about setting up a fast rise time clock signal with a large series resistor to each jtag pin. Then i can try to detect the gate capacitance on a scope. Afaik unconnected balls are pretty unlikely, but shorts are more likely. In my design tms and tck are only next to gnd and nc pins. They are definately not shorted to ground. Somewhere i read that any assertion of tms should make tdo come out of highz. Is that true?

All vcco are powered with 3.3 and vccc is 1.8. The rails measure correctly. The chip seems to be working as it is ever so slightly warm while running and some things work. Like done is actively pulled low. Also, when the chip does it;s restting while writing the prom, it is able to source and sink current.

It would be really hard to change the mode pins. My next board might have this as an option. Instead, i removed the prom and am now feading the fpga's tdi directly from my programmer.

Is it possible that my programmer was supplying a clean enough tck/tms for the prom but not for the fpga? It seems like even dirty signals would cause tdo to be asserted in some way.

Thanks, Jon Pry