Field-Programmable Gate Arrays

Virtex 4 Config

Hi Could someone just confirm for me that I can connect the config block t 3.3V in a Virtex 4 device. I have checked th...

4 comments posted 19yrs

posted by maxascent

4 comments posted 19yrs posted by maxascent

Newbie questions: Can I do this PLL all digitally in a FPGA? 8Khz clock locked on a 100hz pulse

Can I do this all in a FPGA? I would like to sync to an incoming pulse (its actually going to be a register write) that...

5 comments posted 19yrs

posted by ZR1TECH

5 comments posted 19yrs posted by ZR1TECH

Frogger and Scramble released

Pleased to announce the release of Frogger and Scramble (with source code) at www.fpgaarcade.com. Enjoy....

2 comments posted 19yrs

posted by mikej

2 comments posted 19yrs posted by mikej

programming virtex2 FPGA

I have generated a .bit file and try to program xc2v3000 FPGA but through impact gives a message that checking done pin...

4 comments posted 19yrs

posted by jrgodara

4 comments posted 19yrs posted by jrgodara

KCAsm beta

Hello group. As some of you requested it, I have updated the KCAsm pico/pacoblaze assembler. The new version supports r...

0 comments posted 19yrs

posted by pablobleyer

0 comments posted 19yrs posted by pablobleyer

Virtex 5 static and dynamic (re)configuration

Hi, Could someone explain me briefly which is the basic difference between static configuration and dynamic reconfigura...

1 comments posted 19yrs

posted by piclist9

1 comments posted 19yrs posted by piclist9

Stolen Spartan 3E-1600 Development Board

My apologies to those who'd consider this spam, but my house in Milpitas, CA was burglarized and among the less mainstr...

4 comments posted 19yrs

posted by tommy.thorn

4 comments posted 19yrs posted by tommy.thorn

Virtex-4 pre-configuration pull-ups

I can't seem to find any data on the value of the "weak" pull-ups on the IO pins during configuration if the HSWAPEN pi...

5 comments posted 19yrs

posted by nobby

5 comments posted 19yrs posted by nobby

XIlinx tools question - how to quickly identify unconstrained paths

I trying to integrate an IP block from a client and it has a ton of clock crossing, most of which are probably OK. Up t...

4 comments posted 19yrs

posted by johnp3+nospam

4 comments posted 19yrs posted by johnp3+nospam

Programming Question

S/w used : Xilinx WebPack Chip : Spartan - XC2S200PQ208C I have configured a bus as a bi-direction by declaring it as '...

3 comments posted 19yrs

posted by rohan.jyrm

3 comments posted 19yrs posted by rohan.jyrm

TDM stream multiplex/demultiplex

Would anyone know if there is a core out there that can multiplex 4 2.048MHz TDM streams onto 1 8.192MHz stream? (and i...

0 comments posted 19yrs

posted by jai.dhar

0 comments posted 19yrs posted by jai.dhar

xilinx spartan3e kit ddr sdram

Hi all, is there any open source DDR SDRAM controller IP available (VHDL) for the DDR SDRAM on this kit ?

2 comments posted 19yrs

posted by emu

2 comments posted 19yrs posted by emu

Apart from IEEE, is there some another journals for publishing an FPGA article?

Hi, I would like to know if someone could recommend me some journal for publishing my article about FPGA.

2 comments posted 19yrs

posted by pbantunez

2 comments posted 19yrs posted by pbantunez

UK shop - FPGA boards + chips.

Hi, Is there a UK site where I can get FPGA boards (particularly aimed at Spartan3 series) and the FPGAs? Thanks, Nick.

3 comments posted 19yrs

posted by NickHolby

3 comments posted 19yrs posted by NickHolby

Power consumption problem

Hi, when i implemented my architecture using ACTEL AFS600 (Fusion family) i noticed that over 16MHz there is a gap in c...

4 comments posted 19yrs

posted by Amine.Miled

4 comments posted 19yrs posted by Amine.Miled