Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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UK shop - FPGA boards + chips.
Hi, Is there a UK site where I can get FPGA boards (particularly aimed at Spartan3 series) and the FPGAs? Thanks, Nick.
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16 years ago
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Power consumption problem
Hi, when i implemented my architecture using ACTEL AFS600 (Fusion family) i noticed that over 16MHz there is a gap in consumption, in fact when i was changing my frequency from 1 kHz to 16 Mhz the...
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16 years ago
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Optical RocketIO
I've been using a certain make of fibre-optic transceiver to provide optical RIO connectivity at the full 3.125Gbps rate. The manufacturer has dropped the parts I've been using and I'm now looking for...
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16 years ago
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Help with T-VPACK
Hello, I need help with using T-VPACK. I have been having trouble getting T- VPACk to accept the blif files I've been writing or generating from verilog files using the steps found on this board. I...
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16 years ago
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EDK Sim: BRAM won't init
Ugggggghhhhhhhhhhhhhhhhhhhhhhh!!!!!! I HATE UPGRADING XILINX TOOLS!!! Seems like every time we do, there are days of pain involved. I have a sim that used to work in 8.2 that now does not work in 9.1....
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16 years ago
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Unexpected resources utilization
I am programing a 8-channel digitizing board based on xc3s400 and I ran into the following situation: Here are peaces of code that I think might make it easier to understand: COMPONENT ADC_Channel...
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16 years ago
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Unused clock pins tied inactive?
I'm doing a PCB design for a client which incorporates a Cyclone II. I have only used two of the 8 dedicated clock pins so had left the rest floating. During a schematic review one of the client's...
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16 years ago
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Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
Hi, I have a program which needs to allocate high memory with calloc, but I want to load the app on the BRAM, so I wish to configure linker script so heap resides on the SDRAM. Is it possible?. Does...
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16 years ago
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EDK 9.1 + Virtex 5 Hard MAC
Hello All, I'm learning how to use Xilinx EDK, but am stuck... I figured out how to create a simple Microblaze system which uses the opb_ethernet IP core, but I would like to switch to the hard MAC on...
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16 years ago
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synthesis - design compiler or synplify pro?
Hi there, I'm trying to think hard how design compiler and synplify pro differ with each other from a user's point of view, for example, synthesizing for xilinx virtex fpga. Any inputs would be...
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16 years ago
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How to put part of program data into local ram, the rest into external memroy?
Hi guys, I have a question regarding how to use linker script to place specific data in the specific memory. Lets make long story short. Assume I have four arrays: a[100], b[100], c[1000], d[1000] in...
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16 years ago
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DVI-D Tx directly from FPGA?
If you ever spot ( or need help writing/testing ) a FPGA DVI transmitter, let us know! I've been thinking about trying that for a small S3E home project; lots of colo{u}rful pixels with only a few...
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16 years ago
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Re: Altera FPGA programming problem.
Can someone help? "lyra" ?ÈëÏû?ÐÂÎÅ:f4ai3m$5av$
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16 years ago
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ANNOUNCE: Atom 2007.06
Atom is a high-level hardware description language embedded in Haskell that compiles conditional term rewriting systems into conventional HDL. New in this release: - User guided rule scheduling to...
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16 years ago
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Spartan3A-DSP Development Board
Once again we are producting some new development board products this time around the Spartan3A-DSP family. Given the positioning of this chip I would be interested in what you guys out there would...
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16 years ago
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