Field-Programmable Gate Arrays

high voltage input on SPARTAN-3 FPGAs: MTBF reduction?

After some search on this group, at the internet and at Xilinx web site I have not found a conclusive set of informatio...

15 comments posted 19yrs

posted by aee

15 comments posted 19yrs posted by aee

cosimulation

I am prototyping a IP core which was written in verilog languge in cyclone II FPGA.My application engineer wrote code i...

1 comments posted 19yrs

posted by vsrpkumar

1 comments posted 19yrs posted by vsrpkumar

Can I use chipscoe to look at V5 GTPoutputs

I would like to know if I can use Chipscope to look at the V5 GTP outputs. I am using 4 GTP outputs at 3.125 Gbps and wa...

2 comments posted 19yrs

posted by

2 comments posted 19yrs posted by

Choosing the EPC16 or the EPCS64 for Stratix II

Hello, I'm trying to decide to use an EPC16 or EPCS64 to program the Stratix II EP2S601020C3 on my board. Can any comme...

7 comments posted 19yrs

posted by jjlindula

7 comments posted 19yrs posted by jjlindula

About the parallel port jtag programmer,

About the parallel port jtag programmer, can anyone say what is the reason we require resistors at the inputs to the buf...

1 comments posted 19yrs

posted by <darrick>

1 comments posted 19yrs posted by <darrick>

Xilinx ISE + Multi CPU setup?

Does Xilinx ISE benefit from Multi CPU setups? Like offered by AMD Athlon64 X2, AMD Opteron, Intel Core2Duo etc..? Also...

5 comments posted 19yrs

posted by pbFJKD

5 comments posted 19yrs posted by pbFJKD

32bit multiplication in a PowerPC405 of a VirtexIIPro

Hello, I would like to do a 32bit multiplication. The result must be stored in a "64bitregister". I did that : Xuint32...

7 comments posted 19yrs

posted by lpaulo07

7 comments posted 19yrs posted by lpaulo07

s3a kit - Use sma as signal output ?

Is it possible to use the sma connector on the s3a or s3e boards as a signal output not just a clock output ? I haven't...

3 comments posted 19yrs

posted by news

3 comments posted 19yrs posted by news

Question about xilinx programmer

In the xilinx programmer diagram (jtag/parallel download cable) (0380507) there is note number 2 which tells us that d6...

2 comments posted 19yrs

posted by <darrick>

2 comments posted 19yrs posted by <darrick>

intermitent boot in V4

I have an SOC design built in EDK 8.2.03 for a v4fx12. The fpga boots from an xcf08p serial prom. I have an intermitten...

4 comments posted 19yrs

posted by cepope

4 comments posted 19yrs posted by cepope

Multiplier in Xilinx

I have a problem about the data width of the output of multiplier. I am using the coregen Multiplier in Xilinx. a : std...

11 comments posted 19yrs

posted by threeinchnail

11 comments posted 19yrs posted by threeinchnail

Why PLL and not DCM for V5?

I would like to know why the coregen software uses the PLL to generate the two user clocks - one for the GTP and one fo...

2 comments posted 19yrs

posted by

2 comments posted 19yrs posted by

How to pass several commands inside xps from script?

Does somebody know how to execute (pass) several commands inside xps? Now I invoke xps from a batch file through xps -n...

2 comments posted 19yrs

posted by zlatkopetrov

2 comments posted 19yrs posted by zlatkopetrov

Xilinx programmer, many unknown devices...

I would like to ask some questions regarding a Xilinx JTAG programmer: First, it seems that the programmer doesn't actu...

9 comments posted 19yrs

posted by <darrick>

9 comments posted 19yrs posted by <darrick>

Virtex5 LXT Clock Distribution

I am using four GTP transceivers of V5 LXT 110T FPGA. I used coregen to create the verilog output. When I looked at the...

0 comments posted 19yrs

posted by

0 comments posted 19yrs posted by