Why PLL and not DCM for V5?

I would like to know why the coregen software uses the PLL to generate the two user clocks - one for the GTP and one for the fpga fabric? There are very limited number of PLLs so why not use the DLL for this task?

Eddie

Reply to
Eddie H
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I haven't looked at V5 GTPs or PLLs for that matter at all yet. So, what follows is just a guess... Maybe jitter spec for PLL is better? Or maybe you choose a frequency that can't be produced with a DLL?

/Mikhail

Reply to
MM

Mikhail,

Good guess. The V5 PLL does attenuate jitter, so to get the best possible, lowest jitter clock, this is the choice. Not using the PLL will most likely work just fine, it is just that one would have to verify that the transmit jitter was within whatever applicable specification. As well, the receive input jitter tolerance would also have to be verified.

Check the characterization reports for the standard(s) of interest, and see how the tests were done. If they used the V5 PLL, then if you do not use it, you should repeat these tests (to be sure your source clock is good enough). If they did not use this resource, then no issue.

I haven't checked these out, so I will go do a little light reading.

Austin

Reply to
austin

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