In the xilinx programmer diagram (jtag/parallel download cable) (0380507) there is note number 2 which tells us that d6 busy and pe are connected at the db25 end of data cable. What does that mean? where is the db25 end? What will happen if I will connect it on the pcb instead? Thanks in advance
p.s. Anyone knows what is the purpose of d1 and d2 and c1 to c4 and r9 to r12 and r3 to r7 and r1/r2/r14/r8/r13/c5 Basically, it would be nice to have a list of all the components along with their "rason de etre" (feel free not to answer this p.s.)