Field-Programmable Gate Arrays

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ICAP in Virtex 4

Hello, Has anyone succeeded to do module based, dynamic partial reconfiguration in a Virtex4 Device with the ICAP? I am...
0 comments posted 19yrs
posted by fabians
0 comments posted 19yrs posted by fabians

Xilinx, converting ncd back to edif

Hello everyone, I have a placed and routed .ncd file and I'd like to be able to convert it back to a simple netlist. It...
6 comments posted 19yrs
posted by tnt-at-246tNt-dot-com
6 comments posted 19yrs posted by tnt-at-246tNt-dot-com

XMD crashes on EDK 9.1i

Hello Group Members I am trying to build a simple system consisting of PowerPC405, JTAG, UART, OPB DDR controller, and...
1 comments posted 19yrs
posted by swamydp
1 comments posted 19yrs posted by swamydp

Why is Xilinx XPS 8.2i so slow?

Gang I created a half dozen example projects using ISE 8.2i and the PicoBlaze on my S3-1600 Dev Board. I'm really comfo...
2 comments posted 19yrs
posted by bob.zigon
2 comments posted 19yrs posted by bob.zigon

Timing simulation

I would like to know how to have easy access to the internal state machines and registers in its ennitrity while doing...
7 comments posted 19yrs
posted by
7 comments posted 19yrs posted by

Xilinx VHDL multidimensional array synthesis

Hello, I was working on a video font which I initially did as a 2 dimensional array of std_logic_vectors, one dimension...
5 comments posted 19yrs
posted by bradsmallridge
5 comments posted 19yrs posted by bradsmallridge

EDK Microblaze project without OPB?

Hi, all. Is it known to be possible to create a Microblaze system without the OPB? For example, say I have 1 MicroBlaze...
2 comments posted 19yrs
posted by the.jd.in.space
2 comments posted 19yrs posted by the.jd.in.space

Anyone know any good vhdl ethernet tutorials?

I don't know that my fpga is capable (spartan 3e 100k), but I thought I might like to try to do ethernet first. I remem...
2 comments posted 19yrs
posted by john.m.oyler
2 comments posted 19yrs posted by john.m.oyler

Virtex-5 and powerpc

I cannot find any reference to powerPC cores in any of the Virtex-5 datasheets. The only reference to PowerPC in those...
6 comments posted 19yrs
posted by janbeck
6 comments posted 19yrs posted by janbeck

PC104+ communication with FPGA using Xilinx IPCore

Hi, I was wondering if anyone has ever use FPGA to communicate with another board that use PC/104 plus bus as the inter...
3 comments posted 19yrs
posted by ameliaw.azman
3 comments posted 19yrs posted by ameliaw.azman

Beginners question

Dear Group, I have a xilinx xc9536 , a 22 bit counter, and a 5 bit counter. The 22 bit counter is used as a 48mhz clock...
16 comments posted 19yrs
posted by <Tonico>
16 comments posted 19yrs posted by <Tonico>

verilog parser question about `defines

I have a set of verilog files that uses `defines. The same `define is applied to each file to select which code to use....
3 comments posted 19yrs
posted by raphfrk
3 comments posted 19yrs posted by raphfrk

pci express pinout

Would anyone here know the history of pin B3 on the pci express connector? The latest PCISIG document shows it as +12V...
3 comments posted 19yrs
posted by colin_toogood
3 comments posted 19yrs posted by colin_toogood