Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Altera or Xilinx
Hi all, For a new project we will need an FPGA and need to select one, so the question is: Altera or Xilinx? At least, it is my impression that those two are the major fpga companies today. Or did I...
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16 years ago
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Xint64 ?
Hi everybody, I'm using XPS/EDK with a MicroBlaze design and in my code I need a 64- bit wide variable. Is it possible in to define something like Xint32 but for 64bit? I know that the underlying...
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16 years ago
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tiny Spartan 3 module?
Does anyone sell a very tiny board with a Spartan 3 (or 3E, 3A, 3AN) and regulators to run from a 3.3V supply? I only need a handful of 3.3V CMOS I/O pins, but the whole module needs to be really...
9
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16 years ago
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9 | |
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Aldec ActiveHDL vs. ModelSim
I currently use Altera Quartus along with ModelSim for FPGA designs using Verilog. In ModelSim I use the "$random" term to create a random driver. My company is considering updating its tools so that...
1
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16 years ago
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Spurious NULs using uartlite
Hi there, I have a Xilinx university program Virtex-II board and I'm trying to get my head round the serial port on it. I am using EDK and implementing a C program on a MicroBlaze, and using EDK's...
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16 years ago
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3 input adder in Spartan 3E
Hi, I have to design with 3 input adder, i.e. D = A + B + C, in Spartan 3E. The addition has to be finished in one 153.6MHz clock. When I do PAR, I met timing violations. Can anybody give me some...
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16 years ago
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Arming the Chipscope Pro ILA
Hi, I have to record some events immediately atfer configuration of my FPGA (Spartan-3 1500). Chipscope's ILA and ICON are included and work well. Unfortunately, I'm not fast enough to hit F5 in time...
3
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16 years ago
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hard_temac : mdio conflict
Hi everybody, I've a problem with the mdio_0 signal of the hard temac available in the virtex4. Writting to the PHY is good but reading gives erroneous results. With an oscilloscope I can see that the...
9
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16 years ago
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ise 9.2 fatal error
hello, we are trying to compile a v5 sx95t running 9.2 on linux red hat 9, but we are unable to pass the map step (ngdbuild went fine) any clue ? cheers Vincent Release 9.2.01i - Map J.33 Copyright...
1
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16 years ago
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Corgen Adder Vs DSP48 Adder in Virtex4
Hello. I now have 53bit corgen adder in my design. In order to upgrade the speed, I will do something about 53 bit adder. so Is there anyone who know which one between Corgen and DSP48 is faster? ps...
3
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16 years ago
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Connecting Bram LMB Controller to Microblaze
Hello, I have a block ram in my edk is connected to lmb bra controller.I want to connect this controller to i need a another lmb bus to connect microblaze or can i connect lmb controller t microblaze...
8
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16 years ago
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VCD file doesn't show anything in GtkWave
Hi: I have used Icarus Verilog 0.8.4 on Suse Linux 9.1 to create a .vcd file from a testbench. The .vcd file is shown below. I also installed GtkWave 3.0.29 and used the command: > gtkwave to attempt...
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16 years ago
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Bizarre Xilinx configuration problem
Bringing up a new FPGA board I have encountered a very bizarre problem: If I enable a specific pin as an output, the FPGA fails to configure. This pin can be grounded, tied high, or used as an input...
3
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16 years ago
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DDR2 w/ MIG on Xilinx ML501 Board
Hello - I am trying to use the Xilinx MIG version 1.72 to generate a working interface for the DDR2 memory on the Xilinx ML501 eval board. I am having a bit of trouble. I am able to simulate the...
4
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16 years ago
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IOSTANDARD LVDS_25 Error after upgrade to ISE 9.2i
Hey everyone, I just recently upgraded from ISE 8.2i to 9.2i (service pack 1) and now i'm getting an error in my UCF file. Error appears while running map. ERROR:Pack:946 - The I/O component...
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16 years ago
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