hard_temac : mdio conflict

Hi everybody, I've a problem with the mdio_0 signal of the hard temac available in the virtex4. Writting to the PHY is good but reading gives erroneous results. With an oscilloscope I can see that the voltage does not excess 1V (3.3V expected) during the read phase, during write phase I have 3.3V. A conflict with the FPGA is possible because the PHY is alone on the management bus. Is it possible that the tristate into the FPGA does not work ? Any ideas ? Thank you.

Reply to
Paul
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Paul,

Bonjour,

Il est meilleur si vous ouvrez un 'web case':

formatting link

Vous recevrez une réponse beaucoup plus rapidement...

Aust> Hi everybody, I've a problem with the mdio_0 signal of the hard temac

available in the virtex4. Writting to the PHY is good but reading gives erroneous results. With an oscilloscope I can see that the voltage does not excess 1V (3.3V expected) during the read phase, during write phase I have 3.3V. A conflict with the FPGA is possible because the PHY is alone on the management bus. Is it possible that the tristate into the FPGA does not work ? Any ideas ? Thank you.

Reply to
austin

Your PHY is expecting a pullup resistor on the bus.

/Mikhail

Reply to
MM

there is a pullup on the bus. I made another test: decreasing the drive strength of the FPGA from 12mA to 2mA allow MDIO to reach 3.3V ...

Reply to
Paul

What's the value of your pullup? I haven't looked at this pin with a scope but my design is working fine with 4mA drive, 2.1K pullup, 2.5 V voltage, and a VSC8201 PHY...

/Mikhail

Reply to
MM

the pullup's value is 2K, 3.3V the PHY is a DP83865 from NSC.

(thank's for the help).

Reply to
Paul

Apparently not when the Webcase system is down for maintenance.

------------------------------------------------------------------------------------------------------------------- To: snipped-for-privacy@shapes.demon.co.uk Subject: Case 694071 has been registered with Xilinx Application Support From: Xilinx Technical Support Date: Thu, 19 Jul 2007 12:24:18 -0700 (PDT)

-------------------------------------------------------------------------------------------------------------------

No further correspondence as of 1pm UTC 25 July.

- Brian

Reply to
Brian Drummond

I made another test today, I put the MDIO_0_T signal on a testpoint available on my board. It goes high only during the turn-around bit! I guess it should be high during the read phase also.

I have opened a webcase, wait and see ...

Reply to
Paul

Brian,

I am also recently (last two weeks) disappointed in the Xilinx website availability. There have been some breakdowns with our provider, and we are also transitioning to a whole new web site content management system.

A bit like replacing the engine on an airplane while flying.

I have to use it as well! In fact, to get answers, I file a webcase. It is faster than any other method (unless I know exactly who has the answer, in which case I may call them, or email them. But with ~ 3,000 employees, that is pretty hard to do).

I apologize in advance for any difficulties, but please continue to check back: it will be back, and be back better than before.

Austin

Reply to
austin
[re: webcase]

I sincerely hope you get better turnround times!

I heard back from Xilinx; it will be assigned to an engineer today.

- Brian

Reply to
Brian Drummond

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