DDR2 w/ MIG on Xilinx ML501 Board

Did you do a behavioral simulation? Do a post-PAR simulation and check if the initialization still completes.

Also did you change the controller to work with the ML501? The ML501 has a SODIMM device on it. Check the following link on information on how to change the controller to work with a SODIMM memory:

Jaco

memory:

Hi Jacob,

Thanks for the reply. I did see the notes on using SODIMMs and believe I have followed it correctly. I also appropriately modified the testbench provided with the MIG output - 4 memory modules with 16-bit datawidth, etc.

I had not run a simulation beyond behavioral. I ran a post-PAR sim this afternoon and it seems to still simulate correctly (i.e. phy_init_done) is asserted after ~42us.

I did see some error messages in the modelsim terminal window though:

# ** Error: /afs/csail.mit.edu/proj/redsocs/ISE9.1/verilog/mti_se/ simprims_ver/simprims_ver_source.v(102504): $setup( posedge DI[45] &&& (wren_enable == 1):3407202 ps, posedge WRCLKL:3407664 ps, 465 ps );

...and later on...

# ** Error: /afs/csail.mit.edu/proj/redsocs/ISE9.1/verilog/mti_se/ simprims_ver/simprims_ver_source.v(100215): $setup( negedge DDLY:

Not sure if these indicate the simulation isn't running properly or what, but perhaps you can inform me faster than I can figure it out.

Any sense on where to go now? Is there a design that is known to work on the ML501? I don't really want to use the EDK.

Thanks, Ben

memory:

After my post-PAR simulation checked out I decided to check my sanity and try loading my bitfile on another eval board. It worked! (or at least phy_init_done gets asserted). Then I reseated the DIMM on the board I'd been using and it works too. So I guess things are solved for the moment.

Thanks for the help.

Ben

memory:

Came across a weird problem -

I realized that when I was generating the bit file for the ML501 (which seemed to function correctly) I still had the SIM_ONLY parameter (which disables the 200us start-up delay) set to 1. Things had been working fine anyway, but I decided to set it to the proper value of 0. When I do this, the phy_init_done line still gets asserted, but the error line from the synthesizable testbench also is asserted. Disabling the 200us delay makes the signal on the error line disappear. This doesn't make a whole lot of sense to me...

I guess I can run the MIG core with the SIM_ONLY flag forced to 1 since it seems to work, but its a little unsettling to say the least.

Any ideas?

Thanks, Ben