Latest threads in Field-Programmable Gate Arrays

tiny Spartan 3 module?

Does anyone sell a very tiny board with a Spartan 3 (or 3E, 3A, 3AN) and regulators to run from a 3.3V supply? I only n...

9 19yrs

eric

9 19yrs eric

Aldec ActiveHDL vs. ModelSim

I currently use Altera Quartus along with ModelSim for FPGA designs using Verilog. In ModelSim I use the "$random" term...

1 19yrs

spgoldman

1 19yrs spgoldman

Spurious NULs using uartlite

Hi there, I have a Xilinx university program Virtex-II board and I'm trying to get my head round the serial port on it....

0 19yrs

philip.g.potter

0 19yrs philip.g.potter

3 input adder in Spartan 3E

Hi, I have to design with 3 input adder, i.e. D = A + B + C, in Spartan 3E. The addition has to be finished in one 153....

15 19yrs

chenyong20000

15 19yrs chenyong20000

Arming the Chipscope Pro ILA

Hi, I have to record some events immediately atfer configuration of my FPGA (Spartan-3 1500). Chipscope's ILA and ICON...

3 19yrs

tom.reinemann

3 19yrs tom.reinemann

hard_temac : mdio conflict

Hi everybody, I've a problem with the mdio_0 signal of the hard temac available in the virtex4. Writting to the PHY is...

9 19yrs

paul.peronnard

9 19yrs paul.peronnard

ise 9.2 fatal error

hello, we are trying to compile a v5 sx95t running 9.2 on linux red hat 9, but we are unable to pass the map step (ngdb...

1 19yrs

califrancais

1 19yrs califrancais

Corgen Adder Vs DSP48 Adder in Virtex4

Hello. I now have 53bit corgen adder in my design. In order to upgrade the speed, I will do something about 53 bit adde...

3 19yrs

lkjrsy

3 19yrs lkjrsy

Connecting Bram LMB Controller to Microblaze

Hello, I have a block ram in my edk design.It is connected to lmb bra controller.I want to connect this controller to m...

8 19yrs

mfgunes

8 19yrs mfgunes

VCD file doesn't show anything in GtkWave

Hi: I have used Icarus Verilog 0.8.4 on Suse Linux 9.1 to create a .vcd file from a testbench. The .vcd file is shown b...

11 19yrs

crcarleRemoveThis

11 19yrs crcarleRemoveThis

Bizarre Xilinx configuration problem

Bringing up a new FPGA board I have encountered a very bizarre problem: If I enable a specific pin as an output, the FP...

3 19yrs

pcw

3 19yrs pcw

DDR2 w/ MIG on Xilinx ML501 Board

Hello - I am trying to use the Xilinx MIG version 1.72 to generate a working interface for the DDR2 memory on the Xilin...

4 19yrs

bgelb.mit.edu

4 19yrs bgelb.mit.edu

IOSTANDARD LVDS_25 Error after upgrade to ISE 9.2i

Hey everyone, I just recently upgraded from ISE 8.2i to 9.2i (service pack 1) and now i'm getting an error in my UCF fi...

0 19yrs

robquigley

0 19yrs robquigley

On I2C protocol

As for the I2C Master, assuming no clock stretching is issued by the Slave, here is a common situation and its concerni...

15 19yrs

me

15 19yrs me

help: buggy IDE driver on Intel IXP425 GPIO(EXPB)

I have to use this ide vhdl driver that's supposed to link an IDE channel to the expansion bus of an IXP425 Intel proce...

0 19yrs

metiu.uitem

0 19yrs metiu.uitem