Field-Programmable Gate Arrays

doubts

Hai all, I am having the following questions in SDIO : Which register will decide the mode as DMA or Normal mode? Wat d...

0 comments posted 19yrs

posted by fazulu.vlsi

0 comments posted 19yrs posted by fazulu.vlsi

regarding the post PnR timing simulation.....

hi all, i have done the post place and route timing simulation for my design. i am getting the following warnings . the...

3 comments posted 19yrs

posted by jackkilb

3 comments posted 19yrs posted by jackkilb

completely open source fpga toolchain

Please bear in mind that this is only an 8-bit ripple-carry adder, and the tools are still quite crude, but I believe w...

9 comments posted 19yrs

posted by megacz

9 comments posted 19yrs posted by megacz

MS 6.2 code coverage report

Hi, I am facing a strenge problem in using Model Sim 6.2 code coverage report generation CLI. e.g. I have a modular des...

0 comments posted 19yrs

posted by akhileshpatil

0 comments posted 19yrs posted by akhileshpatil

X values in ASIC

Hi, I just overheard about a kind of standard lib component F/F, which are used to "smash" X-values at the module level...

3 comments posted 19yrs

posted by akhileshpatil

3 comments posted 19yrs posted by akhileshpatil

why my usb cable can established,but can't download??? xilinx

hi, all: i install ise9.1 in my gentoo linux. i connect usb cable and run the impact. it displayer the error informatio...

0 comments posted 19yrs

posted by lqjogq

0 comments posted 19yrs posted by lqjogq

Best CPU platform(s) for FPGA synthesis

OK, the questions apply primarily to FPGA synthesis (Altera Quartus fitter for StratixII and HardCopyII), but I'm inter...

38 comments posted 19yrs

posted by jjohnson

38 comments posted 19yrs posted by jjohnson

DCM with Xilinx Spartan 3E and Precision

Hello everyone, I would like to use an DCM in a Xilinx Spartan 3E device. The synthesis is done with Mentor Graphics Pr...

3 comments posted 19yrs

posted by fras

3 comments posted 19yrs posted by fras

Is my microblaze cache functioning?

Hello all, I am using a Spartan 2E 600-LC development board. When I created the project using the BSB I did not specify...

1 comments posted 19yrs

posted by markmcmahon

1 comments posted 19yrs posted by markmcmahon

plb_temac with lwip and sgdma

Hi, is there any documentation for using plb_temac and lwip with the DMA enabled in plb_temac ? Thank's. Paul.

0 comments posted 19yrs

posted by

0 comments posted 19yrs posted by

Problem with X_FF primitive acting as a latch instead of a fliflop

Hi alls, I've a amazing problem in my virtex XC2V1000 design. I've verilog code which normaly should generate a D flipF...

9 comments posted 19yrs

posted by michel.talon

9 comments posted 19yrs posted by michel.talon

LogicSim 3.1 Verilog Simulator Released!

Hi there, I'd like to announce the release of LogicSim 3.1. This is a maintenance and support release that addresses so...

0 comments posted 19yrs

posted by ngsayjoe

0 comments posted 19yrs posted by ngsayjoe

Programing Vertex 4 FPGA by PIC

Hi all I am trying to program the Vertex 4 FPGA (XC4VFX100) in the slave serial mode using a PIC. I am facing a problem...

1 comments posted 19yrs

posted by ramaarchana

1 comments posted 19yrs posted by ramaarchana

ICAP in Virtex 4

Hello, Has anyone succeeded to do module based, dynamic partial reconfiguration in a Virtex4 Device with the ICAP? I am...

0 comments posted 19yrs

posted by fabians

0 comments posted 19yrs posted by fabians

Xilinx, converting ncd back to edif

Hello everyone, I have a placed and routed .ncd file and I'd like to be able to convert it back to a simple netlist. It...

6 comments posted 19yrs

posted by tnt-at-246tNt-dot-com

6 comments posted 19yrs posted by tnt-at-246tNt-dot-com