Latest threads in Field-Programmable Gate Arrays

Xilinx XC3S400-4PQ208C pin name files?

Where on does one find those files with pinname files? Like this: 1 GND 2 IO_7 207 PROG_B 208 TDI etc.. I know this was...

3 19yrs

pbFJKD

3 19yrs pbFJKD

Can Xilinx and Altera be on the same JTAG chain for programming?

If I put a Xilinx SysAce and two Altera Stratix II FPGAs on the same JTAG chain, will I be able to program the two Alte...

1 19yrs

dale.prather

1 19yrs dale.prather

doubts

Hai all, I am having the following questions in SDIO : Which register will decide the mode as DMA or Normal mode? Wat d...

0 19yrs

fazulu.vlsi

0 19yrs fazulu.vlsi

regarding the post PnR timing simulation.....

hi all, i have done the post place and route timing simulation for my design. i am getting the following warnings . the...

3 19yrs

jackkilb

3 19yrs jackkilb

completely open source fpga toolchain

Please bear in mind that this is only an 8-bit ripple-carry adder, and the tools are still quite crude, but I believe w...

9 19yrs

megacz

9 19yrs megacz

MS 6.2 code coverage report

Hi, I am facing a strenge problem in using Model Sim 6.2 code coverage report generation CLI. e.g. I have a modular des...

0 19yrs

akhileshpatil

0 19yrs akhileshpatil

X values in ASIC

Hi, I just overheard about a kind of standard lib component F/F, which are used to "smash" X-values at the module level...

3 19yrs

akhileshpatil

3 19yrs akhileshpatil

why my usb cable can established,but can't download??? xilinx

hi, all: i install ise9.1 in my gentoo linux. i connect usb cable and run the impact. it displayer the error informatio...

0 19yrs

lqjogq

0 19yrs lqjogq

Best CPU platform(s) for FPGA synthesis

OK, the questions apply primarily to FPGA synthesis (Altera Quartus fitter for StratixII and HardCopyII), but I'm inter...

38 19yrs

jjohnson

38 19yrs jjohnson

DCM with Xilinx Spartan 3E and Precision

Hello everyone, I would like to use an DCM in a Xilinx Spartan 3E device. The synthesis is done with Mentor Graphics Pr...

3 19yrs

fras

3 19yrs fras

Is my microblaze cache functioning?

Hello all, I am using a Spartan 2E 600-LC development board. When I created the project using the BSB I did not specify...

1 19yrs

markmcmahon

1 19yrs markmcmahon

plb_temac with lwip and sgdma

Hi, is there any documentation for using plb_temac and lwip with the DMA enabled in plb_temac ? Thank's. Paul.

0 19yrs

Problem with X_FF primitive acting as a latch instead of a fliflop

Hi alls, I've a amazing problem in my virtex XC2V1000 design. I've verilog code which normaly should generate a D flipF...

9 19yrs

michel.talon

9 19yrs michel.talon

LogicSim 3.1 Verilog Simulator Released!

Hi there, I'd like to announce the release of LogicSim 3.1. This is a maintenance and support release that addresses so...

0 19yrs

ngsayjoe

0 19yrs ngsayjoe

Programing Vertex 4 FPGA by PIC

Hi all I am trying to program the Vertex 4 FPGA (XC4VFX100) in the slave serial mode using a PIC. I am facing a problem...

1 19yrs

ramaarchana

1 19yrs ramaarchana

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