Field-Programmable Gate Arrays

Fatal Error ISE 9.1

hi, i get this message when i run "map". Using target part "5vlx30ff324-3". Mapping design into LUTs... Running directe...

2 comments posted 19yrs

posted by martin.leibetseder

2 comments posted 19yrs posted by martin.leibetseder

Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)

Hello, We have implemented a variable phase shift in a spartan 3E device. The phase shift can be set with a register. N...

7 comments posted 19yrs

posted by Karel.Deprez

7 comments posted 19yrs posted by Karel.Deprez

Altera Cyclone II and Cyclone III "distributed" RAM?

I looked on Altera's website, but I could not find any description on how distributed (LUT-based) RAM works on the CYcl...

3 comments posted 19yrs

posted by aks

3 comments posted 19yrs posted by aks

Xilinx Webpack 9.2 and Windows 2000 Pro?

On Xilinx's website, Webpack product-description no longer lists Windows 2000 as a supported O/S. I'm currently using W...

7 comments posted 19yrs

posted by aks

7 comments posted 19yrs posted by aks

regarding RTOS in NIOS II

hi everyone i am trying to use RTOS in NIOS processor. After going through its documentation i found that UC/OS2 and UC...

1 comments posted 19yrs

posted by srimankk

1 comments posted 19yrs posted by srimankk

Upgrading from EDK 8.1 to EDK 9.1i

Gang I purchased the MicroBlaze Spartan 3E Development Kit. It comes with a copy of the the EDK 8.1 and uses ISE 8.1 We...

2 comments posted 19yrs

posted by bob.zigon

2 comments posted 19yrs posted by bob.zigon

ASIC Digital Design Blog

Hi All, Please allow me to shamelessly plug my blog. It is relatively new (2-3 months old) and just passed the 5000 vie...

6 comments posted 19yrs

posted by write2nir

6 comments posted 19yrs posted by write2nir

DDR Simulation Model

During my work with the XUP development board another problem occured when I tried to use the on-board DDR-SDRAM. A dat...

13 comments posted 19yrs

posted by sego

13 comments posted 19yrs posted by sego

Xilinx/ModelSim bug ? Clocking headache ...

Hi every one, I had a problem this morning in a functionnal simulation that I finally traced to the unisim library. Bas...

14 comments posted 19yrs

posted by tnt-at-246tNt-dot-com

14 comments posted 19yrs posted by tnt-at-246tNt-dot-com

V5 compared to V2P

I'm looking to update a couple of products from VIIPro to V5 devices. Is there some very rough comparison of the relati...

2 comments posted 19yrs

posted by enquiries

2 comments posted 19yrs posted by enquiries

Looking for PLD with embedded memory

I'm looking a PLD with 5V TTL-compatible I/O that has ~2Mb of integrated memory that can be used as ROM and ~64Kb of in...

12 comments posted 19yrs

posted by pkk

12 comments posted 19yrs posted by pkk

Clarifications Regarding FlexRay Stand Alone Cotroller Interfacing With PIC Microcontroller

Dear All, This is Jegadeesh from Trioz Technologies India Pvt Ltd. We are currently working on a project under FlexRay...

0 comments posted 19yrs

posted by jegadeesh.r

0 comments posted 19yrs posted by jegadeesh.r

Looking for 2 simple Xilinx examples of FSL

Gang I'm looking for 2 examples that use the MicroBlaze FSL bus. The first example would do something like creating a c...

3 comments posted 19yrs

posted by bob.zigon

3 comments posted 19yrs posted by bob.zigon

Help on TRB_DC2 Camera module interface

I am tring to design a video acquisition system. I am usimg the DE1 borad and the compactable TRB_DC2 camera module wit...

4 comments posted 19yrs

posted by srimankk

4 comments posted 19yrs posted by srimankk

Question on using RLOC_RANGE

Hi all, I am trying to tell the ISE tools to place DSP48s belonging to a complex multiplier (generated with coregen) cl...

6 comments posted 19yrs

posted by mbmsv

6 comments posted 19yrs posted by mbmsv