Field-Programmable Gate Arrays

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help on basics of ethernet interface

hi all I am a newibe. i am tring to send bit stream data through ethernet. i am using altera DE2 board. i have my data...
0 comments posted 19yrs
posted by srimankk
0 comments posted 19yrs posted by srimankk

Xilinx Webpack for Linux 64 bit?

Does there exist a 64-bit Linux version of Xilinx Webpack? I see the programming tools are available for Linux as 64-bi...
3 comments posted 19yrs
posted by cole
3 comments posted 19yrs posted by cole

Fatal Error ISE 9.1

hi, i get this message when i run "map". Using target part "5vlx30ff324-3". Mapping design into LUTs... Running directe...
2 comments posted 19yrs
posted by martin.leibetseder
2 comments posted 19yrs posted by martin.leibetseder

Xilinx Webpack 9.2 and Windows 2000 Pro?

On Xilinx's website, Webpack product-description no longer lists Windows 2000 as a supported O/S. I'm currently using W...
7 comments posted 19yrs
posted by aks
7 comments posted 19yrs posted by aks

regarding RTOS in NIOS II

hi everyone i am trying to use RTOS in NIOS processor. After going through its documentation i found that UC/OS2 and UC...
1 comments posted 19yrs
posted by srimankk
1 comments posted 19yrs posted by srimankk

Upgrading from EDK 8.1 to EDK 9.1i

Gang I purchased the MicroBlaze Spartan 3E Development Kit. It comes with a copy of the the EDK 8.1 and uses ISE 8.1 We...
2 comments posted 19yrs
posted by bob.zigon
2 comments posted 19yrs posted by bob.zigon

ASIC Digital Design Blog

Hi All, Please allow me to shamelessly plug my blog. It is relatively new (2-3 months old) and just passed the 5000 vie...
6 comments posted 19yrs
posted by write2nir
6 comments posted 19yrs posted by write2nir

DDR Simulation Model

During my work with the XUP development board another problem occured when I tried to use the on-board DDR-SDRAM. A dat...
13 comments posted 19yrs
posted by sego
13 comments posted 19yrs posted by sego

Xilinx/ModelSim bug ? Clocking headache ...

Hi every one, I had a problem this morning in a functionnal simulation that I finally traced to the unisim library. Bas...
14 comments posted 19yrs
posted by tnt-at-246tNt-dot-com
14 comments posted 19yrs posted by tnt-at-246tNt-dot-com

V5 compared to V2P

I'm looking to update a couple of products from VIIPro to V5 devices. Is there some very rough comparison of the relati...
2 comments posted 19yrs
posted by enquiries
2 comments posted 19yrs posted by enquiries

Looking for PLD with embedded memory

I'm looking a PLD with 5V TTL-compatible I/O that has ~2Mb of integrated memory that can be used as ROM and ~64Kb of in...
12 comments posted 19yrs
posted by pkk
12 comments posted 19yrs posted by pkk

Looking for 2 simple Xilinx examples of FSL

Gang I'm looking for 2 examples that use the MicroBlaze FSL bus. The first example would do something like creating a c...
3 comments posted 19yrs
posted by bob.zigon
3 comments posted 19yrs posted by bob.zigon