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Looking for 2 simple Xilinx examples of FSL

Gang

I'm looking for 2 examples that use the MicroBlaze FSL bus.

The first example would do something like creating a component that adds to numbers together and returns them from the custom ip. The example would explain the steps you need to take thru the XPS (and the ISE) to make this run. The host C program would write the

2 operands to the fifo and read the resulting sum.

In the second example, a host C program would write 3 coefficients and

2 pointers into the SDRAM into the fifo. The custom ip would effectively multiply and accumulate the coefficients against the input buffer. It would write the sum back out to the output buffer.

I've looked at FSL_V20.pdf as well as xapp529. Xilinx really needs to do a better job of creating step by step examples for an important feature like the FSL.

Bob

Reply to
bob.zigon
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Dear Bob,

regarding your request:

example 1: please run EDK 9.1 ip wizard for FSL, it creates the IP, library and test application exactly as you described. Add the ip, add the main C application, compile download and you see your FSL adder IP working, exactly as you described. THIS DOES EXIST already, your example 1 *IS* provided by Xilinx for you to be used.

example 2: I did not understand what you want to do with SDRAM pointer. I guess this is the reason why Xilinx has not prepared this example for you. (means there is something you need todo yourself too)

Antti

Reply to
Antti

It seems you're looking for IP that does automatic SDRAM read/write access. Some custom ip in fact implements memory access. More often however, the memory access part is separated from the rest of a custom ip. That's what DMA controllers are for.

The DMA (direct memory access) controller reads data from memory to an I/O register, where your multiply and accumulate ip accepts it. The DMA controller can also read the result from an I/O register and write it back to memory.

Xilinx certainly has DMA controller examples for the FSL bus. Maybe they have even some arithmetic ip core that approximates what you're looking for. Using two such pieces should get you almost home..

Regards, Marc

Reply to
jetmarc

actually NO - DMA can not be used with FSL bus, as FSL bus is not accessible from the any memory busses in the EDK system. FSL bus is only accessible directly by the CPU using special microblaze instructions, so the transfer to-from FSL must be done by microblaze (not DMA engine)

MCH/XCL are "memory busses" based on FSL, but they are mostly used for cache, of course it is possible to design your FSL/MCH ip and connect it to MCH_SDRAM, in that case this FSL IP would have shared access to system SDRAM

Antti

Reply to
Antti

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