1. Home
  2. Field-Programmable Gate Arrays
  3. Fatal Error ISE 9.1

Fatal Error ISE 9.1

hi,

i get this message when i run "map".

Using target part "5vlx30ff324-3". Mapping design into LUTs... Running directed packing... Constraining slice packing based on guide NCD. Running delay-based LUT packing... FATAL_ERROR:Portability:PortDynamicLib.c:358:1.27 - dll open of library failed due to an unknown reason. Process will terminate. For more information on this error, please consult the Answers Database or open a WebCase with this project attached at

formatting link

Process "Map" failed

Could somebody help me?

Reply to
martin.leibetseder
Loading thread data ...

Martin,

One thing that I noticed in your error message was that your ISE install was in the 'Program Files' folder. This may or may not be related to the error, but I would highly recommend that you install the tools in a directory with no spaces. Try installing to the root as Xilinx_9.1 and see if the error goes away. Repost if the error remains and we can go from there.

-David

Reply to
davide

I have also seen this problem with a design when I turned on timing driven Map. The Xilinx folks said to turn off the "register duplication" option in Map to avoid the problem.

I've only tried this a little bit, so I can't guarantee that this is a useful fix.

John Providenza

Reply to
johnp

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.