Field-Programmable Gate Arrays

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Help on TRB_DC2 Camera module interface

I am tring to design a video acquisition system. I am usimg the DE1 borad and the compactable TRB_DC2 camera module wit...
4 comments posted 19yrs
posted by srimankk
4 comments posted 19yrs posted by srimankk

Question on using RLOC_RANGE

Hi all, I am trying to tell the ISE tools to place DSP48s belonging to a complex multiplier (generated with coregen) cl...
6 comments posted 19yrs
posted by mbmsv
6 comments posted 19yrs posted by mbmsv

Odelay usage in virtex5

I would like to use Odelay primitive to delay a signal generated in the virtex5 fpga fabric. For this I am hoping to us...
3 comments posted 19yrs
posted by hphan
3 comments posted 19yrs posted by hphan

Microblaze Interrupt Handler

Hi All, I'm beginner for Microblaze. I use Spartan3E eval kit. I want to create custom ip and use interrupt. 1 - I crea...
2 comments posted 19yrs
posted by icegray
2 comments posted 19yrs posted by icegray

Simple UDP packets forwarding using lwip sockets

Hello. I have just started working with a Virtex 4 board, and I need to make an application which will be connected on...
0 comments posted 19yrs
posted by ryufrank
0 comments posted 19yrs posted by ryufrank

Xilinx something happening with Spartan-3?

hi I wonder how come is xilinx website at least partially broken whenever I need something? today as example Spartan3 p...
3 comments posted 19yrs
posted by Antti.Lukats
3 comments posted 19yrs posted by Antti.Lukats

Restricting XST parameter widths from .mpd files?

I'm working with a custom verilog core that accepts a small number of parameters, and I'm having a hard time pushing th...
2 comments posted 19yrs
posted by neil.steiner
2 comments posted 19yrs posted by neil.steiner

EDK 9.1.02i warnings flood

Hi! I recently installed EDK 9,1.02i. When I synthesize a project I get thousand of warnings, which is really annoying:...
3 comments posted 19yrs
posted by mega_metty
3 comments posted 19yrs posted by mega_metty

query in byte blaster/signal topic logic analyser

Dear All. I want to see the signals in the EP2C12Q240C8 FPGA for my design inside with several instances..It has EPCS4...
0 comments posted 19yrs
posted by vsrpkumar
0 comments posted 19yrs posted by vsrpkumar

spartan-3e spi problems

Hi, I am having trouble configuring a xc3s250e from a st m25pe20 spi flash rom. Originally init would not go low and th...
3 comments posted 19yrs
posted by jonpry
3 comments posted 19yrs posted by jonpry

Xilinx MIG DDR2 initialization problems

I have used the MIG 1.72 tool to generate a memory interface for the DDR2 SODIMM on the Xilinx ML501 board. It works......
2 comments posted 19yrs
posted by bgelb.mit.edu
2 comments posted 19yrs posted by bgelb.mit.edu

Question about GSR?

Hello, What does GSR pin do, when should I use it? How do I use it? Is it required in every design? Thanks in advance fo...
12 comments posted 19yrs
posted by <tonico>
12 comments posted 19yrs posted by <tonico>

V5 Differential Select I/O

Xilinx V5 supports Differential select I/O data rate upto 1250 Mbps. It supports HT_25, LVDS_25 and may other electrica...
1 comments posted 19yrs
posted by
1 comments posted 19yrs posted by