Field-Programmable Gate Arrays

Xilinx Xilfatfs SystemACE library and partition format

Hi, I have been struggling on a Virtex II Pro in order to make the XilFatFS work properly. What I want to do is use the...

0 comments posted 19yrs

posted by antoine.vernay

0 comments posted 19yrs posted by antoine.vernay

Amount of wire and logic

Dear Since Xilinx does not report wire utilization and technology data, I expect that Given FPGA device family : (1) Th...

27 comments posted 19yrs

posted by pasacco

27 comments posted 19yrs posted by pasacco

DDR/DDR2 controller - core

Hi I want to use in my project (with Spartan3 or Cyclone2) a DDR/DDR2 DIMM module. I have chosen DDR because is avaiabl...

8 comments posted 19yrs

posted by "SwietyMikolaj["

8 comments posted 19yrs posted by "SwietyMikolaj["

I2C master connected and tested with LEON Processor

This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter...

0 comments posted 19yrs

posted by bknpk

0 comments posted 19yrs posted by bknpk

EDK (XPS) - Path problem causing "Generate Libraries and BSPs" to fail...

Hi, I'm using EDK/XPS 9.1.02J on Windows XP. I'm working my way through a through the document tutorial "EDK Concepts,...

0 comments posted 19yrs

posted by pretzel_n_g

0 comments posted 19yrs posted by pretzel_n_g

EDK speed issue

Every time I make a minor change to one of my local pcores I have to do a "Clean Netlist" to ensure that the change is...

7 comments posted 19yrs

posted by fred

7 comments posted 19yrs posted by fred

SystemACE, xilfatfs and feof()

Hi all, I'm doing a project with a Xilinx University Project Virtex-II Pro board. For this I'm using the compact flash...

0 comments posted 19yrs

posted by pgp

0 comments posted 19yrs posted by pgp

Reset and DCM

Hello all, I'm working on a FPGA design that runs in board with a Virtex-II that doesn't have any reset signal. I have...

2 comments posted 19yrs

posted by danielgutierrezcastro

2 comments posted 19yrs posted by danielgutierrezcastro

spartan3 picoblaze how to make .bmm file work

I'm a newbie in fpga design, and am really struggling to create a bmm file that works. I am using an Spartan-3A starter...

4 comments posted 19yrs

posted by bart

4 comments posted 19yrs posted by bart

secure interfacing between an fpga and a connected device

I have - MY_FPGA DEVICE I want to make it so that the DEVICE operates only if MY_FPGA is connected to it. I need to mak...

6 comments posted 19yrs

posted by fpgabuilder-groups

6 comments posted 19yrs posted by fpgabuilder-groups

Xilinx Webpack 9.1: How do I export a netlist to another project?

I've searched Xilnx's website and documentation for help on creating your own IP-cores (for distribution to third-parti...

2 comments posted 19yrs

posted by fpga_engineer

2 comments posted 19yrs posted by fpga_engineer

what the AC exactly short for here...

hi, I can't find the exact mean of AC in this phrase "AC-non-redundant fault" that refered in following abstract: can a...

0 comments posted 19yrs

posted by neil3w

0 comments posted 19yrs posted by neil3w

High Speed ADC

Hi all: I am trying to reconstruct a periodic exponential signal curve. The signal is in the order of 10-20mV. The tota...

3 comments posted 19yrs

posted by cjoseph2

3 comments posted 19yrs posted by cjoseph2

Synthesizing fixed_pkg in ISE 9.2

Hi, I'm trying to synthesize a design with the fixed_pkg package in Xilinx ISE 9.2. I'm using the version adapted for X...

10 comments posted 19yrs

posted by usenet

10 comments posted 19yrs posted by usenet

Specifying LVDS I/O's in Xilinx FPGA's

Hi, Can someone please point me in the right direction. I attempted to define my LVDS inputs via the UCF file for my Xi...

4 comments posted 19yrs

posted by moogyd

4 comments posted 19yrs posted by moogyd