Latest threads in Field-Programmable Gate Arrays

Webpack 9.1 and Samba

I just upgraded? my computer (was W2K) and ISE6.3 to Windows XP and Webpack 9.1 And now have problems with project/work...

2 19yrs

pcw

2 19yrs pcw

embedded tips

Hi all, I've been targeting the general logic of Virtex-2s and Virtex-4s for years now, but I'd like to start getting i...

3 19yrs

ed.agunos

3 19yrs ed.agunos

Xilinx Xilfatfs SystemACE library and partition format

Hi, I have been struggling on a Virtex II Pro in order to make the XilFatFS work properly. What I want to do is use the...

0 19yrs

antoine.vernay

0 19yrs antoine.vernay

Amount of wire and logic

Dear Since Xilinx does not report wire utilization and technology data, I expect that Given FPGA device family : (1) Th...

27 19yrs

pasacco

27 19yrs pasacco

DDR/DDR2 controller - core

Hi I want to use in my project (with Spartan3 or Cyclone2) a DDR/DDR2 DIMM module. I have chosen DDR because is avaiabl...

8 19yrs

"SwietyMikolaj["

8 19yrs "SwietyMikolaj["

I2C master connected and tested with LEON Processor

This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter...

0 19yrs

bknpk

0 19yrs bknpk

EDK (XPS) - Path problem causing "Generate Libraries and BSPs" to fail...

Hi, I'm using EDK/XPS 9.1.02J on Windows XP. I'm working my way through a through the document tutorial "EDK Concepts,...

0 19yrs

pretzel_n_g

0 19yrs pretzel_n_g

EDK speed issue

Every time I make a minor change to one of my local pcores I have to do a "Clean Netlist" to ensure that the change is...

7 19yrs

fred

7 19yrs fred

SystemACE, xilfatfs and feof()

Hi all, I'm doing a project with a Xilinx University Project Virtex-II Pro board. For this I'm using the compact flash...

0 19yrs

pgp

0 19yrs pgp

Reset and DCM

Hello all, I'm working on a FPGA design that runs in board with a Virtex-II that doesn't have any reset signal. I have...

2 19yrs

danielgutierrezcastro

2 19yrs danielgutierrezcastro

spartan3 picoblaze how to make .bmm file work

I'm a newbie in fpga design, and am really struggling to create a bmm file that works. I am using an Spartan-3A starter...

4 19yrs

bart

4 19yrs bart

secure interfacing between an fpga and a connected device

I have - MY_FPGA DEVICE I want to make it so that the DEVICE operates only if MY_FPGA is connected to it. I need to mak...

6 19yrs

fpgabuilder-groups

6 19yrs fpgabuilder-groups

Xilinx Webpack 9.1: How do I export a netlist to another project?

I've searched Xilnx's website and documentation for help on creating your own IP-cores (for distribution to third-parti...

2 19yrs

fpga_engineer

2 19yrs fpga_engineer

what the AC exactly short for here...

hi, I can't find the exact mean of AC in this phrase "AC-non-redundant fault" that refered in following abstract: can a...

0 19yrs

neil3w

0 19yrs neil3w

High Speed ADC

Hi all: I am trying to reconstruct a periodic exponential signal curve. The signal is in the order of 10-20mV. The tota...

3 19yrs

cjoseph2

3 19yrs cjoseph2

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