Since Xilinx does not report wire utilization and technology data, I expect that
Given FPGA device family : (1) There is a constant ratio of INTERCONNECT to LOGIC. (2) When amount of LOGIC increases N times, amount of INTERCONNECT increases N times.
For example : Virtex-II Pro-20 contains 9280 slices and Virtex-II Pro-100 contains44096 slices. That is, Virtex-II Pro-100 contains 4.7 times more slices.
It implies that : In order to realize same ratio of INTERCONNECT to LOGIC, Virtex-II Pro-100 contains 4.7 times more interconnect than Virtex-II Pro 20.
I guess that : The 'AREA' of INTERCONNECT for Virtex--II Pro 100 is MORE THAN 4.7 times larger than Virtex-II Pro.
Question is that Is the AREA of INTERCONNECT for Virtex--II Pro 100 is 4.7 times larger than Virtex-II Pro?