Amount of wire and logic

I think the logic here is flawed.

If there are N elements, and the interconnect is intended to connect form any of the N elements to another of the N elements, then:

if N grows, say it becomes k*N then the M interconnecting elemtns should grow to k*k*M

This should not be taken as excat, but it seems to me that the interconnections don't fgrow lineraly with the logic elements.

Regrads,

Zara

It means.... AREA of interconnects grows super-linearly, as AREA of logic linearly grows. Thank you

I think your logic here is flawed as well.

The local interconnections for each new CLB are replicated (OMUX, DOUBLE, even HEX). The long lines are simply extended though one can look at each CLB having attibuting the X and Y pitch to the next CLB of additional copper for these as well. The high end in a family shouldn't have more resources local to the CLB than the low end of the family, otherwise the software to select the routing could get pretty involved as devices are changed within a family.

The possible destinations increase for each source as the part gets larger, but the structure is still similar around each CLB regardless of size.

- John_H

Everybody would agree that the need for interconnect grows faster than the number of things to be interconnected. Ask any urban planner or any phone company... In FPGAs, the issue is both more complex and also much simpler: More omplex: The interconenct structure in any family consists of a wide varity of different resources; direct connects, single, double, hex lines, long lines, etc. This structure is highly optimized, and is revisited every time we plan a new family. You cannot describe it with just one number. Much simpler: Within a family, the ratio od routing to logic is practically constant, mainly for softwarwe reasons. One cannot create a completely new optimized software structure for every chip size.

Fundamental routability, a big issue years ago, is hardly an issue today. Routing delays are, of course, still an issue, and will always be an issue. The basic elements in an FPGA can be as fast as the ones in the most advanced dedicated chips and ASICs. It's the programmability that slows down the FPGA, but programmability is also its greatest asset... Peter Alfke

Pasacco,

I don't suppose that you have looked at using FPGA_EDITOR?

It would answer your question.

Austin

(P.S. I am always amused at how people 'discover' that FPGA design is not some 'trivial task'... evidenced by the many who have tried to get into the business, and then failed.)

Are you sure about that Peter? I'm sure each house has one telephone wire to the exchange. All the complexity gets moved intot he exchange. So, wires are proportional to number of houses. Also, each house is on one road, has one electricity supply, one gas supply.

Cheers, Syms.

If you want to connect two telephones, you'll need one wire. For three telephone, you'll need a switch and 3 wires. For many more telephones, you'll need a hierarchical system (in the beginning the telephone number digits itself designated the different levels of the hierarchy), if you don't want to connect each telephone with each other. This needs more wires than endpoints, maybe a logarithmic number of additional wires per endpoint, or maybe even more, if you want to handle many parallel connections (I'm not a telephone expert), in addition to the wires from the endpoints, but it doesn't increase proportional.

Analogies often are misleading. The telephone system draws a big benefit from the fact that not everybody wants to talk to everybody else at the same time. (Remember Mr Erlang?) And: a crossbar switch is really a humungously large number of interconnects stuffed in a little box (and nowadays often time-division multiplexed.)

The electricity-gas-water-sewer connections are non-individualized unidirectional busses.

The analogy of urban plann> Sym> > Are you sure about that Peter? I'm sure each house has one telephone wire to

snipped-for-privacy@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de

That's true, but it is still a hierarchical system, which needs more wires than endpoints, with switchers at the different levels, which can route to higher levels, if needed:

So it is not proportional to the number of endpoints, but the additional effort may be small with time multiplexed signals etc.

I wonder if some of these technics could be used for FPGAs as well. There are some designs which doesn't need full speed interconnects and there are designs with loose coupled parts over the chip (but each part could have a high interconnection factor). So e.g. if one part of the chip needs to transfer x bits of data to another part, it could be serialized and even time multiplexed on a global internal bus system.

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1. The high end in a family shouldn't have more resources local to the CLB than the low end of the family.

==>

This means that "how INTERCONNECT is organized" is the same, within same device family. I opend FPGA EDITOR. The CLB structure 'looks' same, for different device, within same family.

1. Everybody would agree that the need for interconnect grows faster than the number of things to be interconnected.

==>

This means that AREA of interconnects grows super-linearly, as AREA of logic linearly grows.

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If yes, my first impression is that : High-end device in a family provides "DECREASED ROUTABILITY" than low- end device in a family.

For example, Virtex-II Pro-100 will provide "DECREASED ROUTABILITY" than Virtex-II Pro-20.

Because: (1) Maximum fan-out that a single wire can drive is 'constant' for different devices. (2) As device size increases, there will be decreased amount of "long distance" wires, when wires are used up for neighbor logics.

What do you want to achieve with these theoretical considerations? As I said, routability is not the problem anymore .. And why do you use 5-year old examples (Virtex-2Pro?) I prefer to address real problems using today's devices... Peter Alfke

Old examples? I wonder what the breakdown is on the number of FPGAs you ship, Virtex-II Pro vs Virtex-4 vs Virtex-5. Since you aren't shipping all the Virtex-5s yet, an I still can't find small unit quatities of Virtex-4s, I bet the Virtex-II Pro is still very relevant.

---Matthew Hicks

Old examples? I wonder what the breakdown is on the number of FPGAs you ship, Virtex-II Pro vs Virtex-4 vs Virtex-5. Since you aren't shipping all the Virtex-5s yet, an I still can't find small unit quatities of Virtex-4s, I bet the Virtex-II Pro is still very relevant.

---Matthew Hicks

Things obviously always look different from the inside than from the outside.

As far as I know, Xilinx has been shipping every member of the three announced Virtex-5 sub-families for awhile. Most of them with the ES designation, but many also as "production". Virtex-4 is shipping in larger volume, since it is used in our customers' production equipment. Virtex-2Pro is doing well, but it is 2 generations behind... AFAIK you can order Virtex-5 parts from the two major distributors, Avnet and NewHorizon. That was a contentious issue a few months ago, that seems to be resolved now. I still have some scars from that internal battle.

I am sorry that I have driven this obscure post> Old examples? I wonder what the breakdown is on the number of FPGAs you

So is there any reason why Xilinx employees that *don't* think that customers should be able to get parts through distribution are still on the payroll? Seems like a good opportunity for Xilinx to cut costs. If you can't fire them outright, send them on the B Ark or something.

I was being (mostly) facetious, as might have been indicated by the reference to the "B Ark" from Hitchhiker's Guide to the Galaxy. I certainly appreciate your efforts at resolving these sorts of problems.

However, it is still annoying that there's no longer a way to easily buy parts in small quantities for prototyping, e.g., XC3S200A-4FTG256CES:

Avnet: no stock, minimum order quantity 17 NuHorizons: in stock, "call for information" (not orderable online)

That was just one part I've tried to get recently, but the situation for many other Spartan 3E, 3A, and 3AN parts is the same.

Somehow other semiconductor vendors manage to do a better job of this. For example, I generally don't have any trouble getting small quantities of TI parts, even for the more obscure, specialized, or recently introduced parts.

The Xilinx Online Store appeared to be an attempt at solving this problem. It was not 100% successful (parts were often out of stock), but it was better than the current situation.

If it's not possible to bring back the online store, perhaps Xilinx could work more closely with Digikey to get them to stock recent parts (e.g., Spartan 3E, 3A, 3AN series). Unlike Avent and NuHorizons, Digikey and Mouser don't mind dealing with small orders.

Thanks, Eric

This is known as Rent's rule

It states essentially that between two portions of the chip that contain g gates you should have T=t*g^p wires. The constants t and p depent on the design. p is typically between 0.5 and 0.8. As a result the number of wires grows at a rate of somewhat over g^1.5 and the area of the wires (because the avarage length is g^0.5) grows faster than g^2

The pathfinder algorithm can cope pretty well with arbitrary networks. However the network needs to be good enough that the placer can assume a decent cost metric.

I did not closely look at the routing architecture for the newer architectures but in the 90s one could clearly see in the FPGA editor that the numer of wires (especially longlines) per routing channel increased with the size of the chip. This is regular enough that any routing algorithm should be able to cope with it.

That is a marketing decision, isn't it?

An FPGA with good routability is more expensive than an FPGA with bad routability. Therefore early FPGAs were wire starved because it economically makes more sense to make good use of the wires and throw away some LUTs that can not be connected.

However as the wires are next to invisible to the designer, everybody kept complaining that not all LUTs could be connected in a larger XC4K. People perceive that as a loss. Therefore all manufacturers switched theire paradigm and added more of those expensive wires. Now all LUTs can be used but the wire utilization is really low.

The good side of this is, that the tool runtime inproves a lot if routing is easy and the performance results are more predictable. But we pay a price.

Kolja Sulimma

It is interesting to see the Rent's rule.

You can help me better understand the relationship.

For example, suppose : Xilinx FPGA has a regular structure of CLBs. Each CLB contains one SWITCH BOX and 4 SLICEs. Each SLICE has approximately 40 pins. Each CLB has approximately 400 pins.

Consider, device 1 has 100 CLBs and device 2 has 10000 CLBs.

According to your posting: Device 2 is supposed to have "100^1.5" times more wires than device 1. Device 2 is supposed to have "100^2" more area than device 1. Am I understanding correctly?

It was mentioned that:

-------------------------------------------------------------- Number of wires grows at a rate of somewhat over g^1.5 and the area of the wires (because the avarage length is g^0.5) grows faster than g^2

--------------------------------------------------------------

Could you please explain why :

(1) Average length is "g^0.5", ==> Does this 'length' mean by "wire length" ? How did you obtain the value '0.5' ?

(2) Number of wires grows over "g^1.5", ==> How did you obtain the value '1.5' ?

(3) Area of wires grows faster than "g^2" ? ==> How did you obtain the value '2' ?

It will be appreciated if you provide some example :). Thank you very much.