Hi all:
I am trying to reconstruct a periodic exponential signal curve. The signal is in the order of 10-20mV. The total length of this curve is
100ns. Even though the total length is 100ns, the peak bandwidth of the signal maybe in the order of 100MHz. I thought about getting only one data point for each period and delay the sampling instance and collect further points (similar to time-interleaved sampling). I have a programmable delay line, which can produce delays in the multiples of 200ps. The goal is to reconstruct the signal curve, no matter how slow the reconstruction is.
I thought about using high speed ADC like ADS5463 from TI, the reason is that it can handle very high Analog input frequency. Or can I use a slower ADC? The sharpness/jitter of the clock-signal and ADC sample/ hold is very important, I feel. Should I consider anything else?
I dont know how could I interface the ADC to collect the digital data. Does FPGA work? Is there any FPGA boards which can be programmed to handle this situation.
Is there any ideas. I am pretty new to FPGA and ADCs.
Thanks, Joe