DDR/DDR2 controller - core

You might want to check out Lattice's XP2 family. Has built-in flash that stores the FPGA configuration which eases design and gives a single- chip, instant-on approach.

Has advanced registering in IO cell to take care of all of the DDR-

path stuff as well as dedicated logic for DQS delay. Lowers LUT count and eases timing - run up to 400Mbps. With 64 bit DRAM interface uses about 2K LUT's (with default values). IPExpress tool provides similar function to Megacore.

I only forgot to mention that im a student and this is an academic project. :) Also I am looking only free solution or these that I can test before purchase like Megacore.

PGW

No. There is no free usefull DDR core.

Precisely. Besides the Spartan 3 DDR controller made by the MIG tool is huge and hopeless. You'll have to be carefull though with connecting too many datalines to a Spartan 3. The power consumption of the IO is huge for driving DDR memory. You'll need an FPGA in a BGA package if you want to connect a DIMM.

Designing a controller is not so difficult if you are after writing/reading bursts of data. A small hint: the DDR controller can be clocked at half the DDR clock frequency.

Even if data rate will by small? I have not consider this aspect before, thanks for advice.

I am not sure I understand this sentence: "if you are after writing/reading bursts of data" What you mean?

PGW

SDRAM, DDR and DDR2 have a minimum clock frequency. This means the datarate cannot be choosen very small.

Designing a memory controller which transfers large blocks of data is much easier (the addresslines are driven by a counter) than a random-access memory controller (address lines need to be translated, transactions must be queued).

As DDR /DDR2 is a pipelined burst memory then you have to be aware of the effect of this on your design. Depending on your data source, you may need another controller to packetise the data into appropriate bursts.

If you have a low data throughput requirement, then it might be easiest to do this in a FPGA based micro core. Certainly Xilinx has DDR 1/2 controllers available that plug onto their micro cores. This would be less error prone than hacking around with a MIG design, unless producing a controller is the main part of your academic project.

Can you tell us any more details about your applciation?

I can not find them, are you sure?

DDR1/2 is not the main part of this project. In my project I want to be able to read two data word (64bits each) form one place in memory and two words from oder place. And similarly at writing. Also with DDR I can use burst 2. Actually a word has 48 bits but I can sacrifice 1/4 of memory to make it easier. And I can use only Spartan3 or Cyclone2 because in oder case using DDR will be not profitable.

PGW

Multi Channel OPB DDR2 Controller The Xilinx Multi-Channel On-chip Peripheral Bus Double Data Rate Synchronous DRAM (MCH OPB DDR2 SDRAM) controller for Xilinx FPGAs provides a DDR2 SDRAM controller that connects to the OPB and multiple channel interfaces and provides the control interface for DDR2 SDRAMs. It is assumed that the reader is familiar with DDR2 SDRAM and the MCH protocol.