I've searched Xilnx's website and documentation for help on creating your own IP-cores (for distribution to third-parties) -- but I didn't find anything. So I'm asking here....
I want to develop an IP-core, and allow FPGA-customers evaluate it. I tried (without success) to synthesize the toplevel module ("my_ipcore"), until I get the .NGC file.
In a brand new Webpack session, different project, I set the toplevel module type from 'HDL' to 'NGC,' I added the .NGC file into the project hierarchy. In the project view, the file seems to register correctly. The test-design "my_test" instantiates 1 instance my_ipcore. When I try to synthesize my_test, Xilinx XST issues the error "cannot find module my_ipcore."
At first, I thought it was a Windows directory/path issue. So I temporarily set the toplevel module to "my_ipcore" The process-flow options change: I no longer have a 'synthesize' command. But If I run through map/place/route, that process starts successfully, proving to me that Webpack can read the my_test.NGC file just fine. (It eventually throws some unrelated errors.)
what's the proper way to generate a netlist? I understand there is no security in a netlist (i.e. it can be used by anyone), but I'm not worried about that right now. I just need a way to give my ip-core to someone else for evaluation, without showing them the source RTL.