Xilinx Webpack 9.1: How do I export a netlist to another project?

I've searched Xilnx's website and documentation for help on creating your own IP-cores (for distribution to third-parties) -- but I didn't find anything. So I'm asking here....

I want to develop an IP-core, and allow FPGA-customers evaluate it. I tried (without success) to synthesize the toplevel module ("my_ipcore"), until I get the .NGC file.

In a brand new Webpack session, different project, I set the toplevel module type from 'HDL' to 'NGC,' I added the .NGC file into the project hierarchy. In the project view, the file seems to register correctly. The test-design "my_test" instantiates 1 instance my_ipcore. When I try to synthesize my_test, Xilinx XST issues the error "cannot find module my_ipcore."

At first, I thought it was a Windows directory/path issue. So I temporarily set the toplevel module to "my_ipcore" The process-flow options change: I no longer have a 'synthesize' command. But If I run through map/place/route, that process starts successfully, proving to me that Webpack can read the my_test.NGC file just fine. (It eventually throws some unrelated errors.)

what's the proper way to generate a netlist? I understand there is no security in a netlist (i.e. it can be used by anyone), but I'm not worried about that right now. I just need a way to give my ip-core to someone else for evaluation, without showing them the source RTL.

Reply to
fpga_engineer
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You are confused with the design flow in ISE.

HDL gets turned into a netlist using XST. Once you have a netlist you can't synthesize it again. It's better to set the top level to HDL and instantiate your core/netlist in the HDL code if you want to test it.

Reply to
naude.jaco

You can also set a "black-box" attribute to the instance of the core in the top-level design. Then XST will not worry about it.

The back end tools (Translate/Map/PAR) need to be able to find the NGC file; either in the project directory or via a search path.

- Brian

Reply to
Brian Drummond

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