Field-Programmable Gate Arrays

Write of 64 from PowerPC to my IP conected to the PLB?

Hello, I have designed a IP Slave connected to the PLB bus. My IP Slave to the PLB is a Bus bridge which connect the PL...

6 comments posted 19yrs

posted by le_marq

6 comments posted 19yrs posted by le_marq

Exception handling code in the OR1200

Recently, I read the source code of OR1200. But I am a little confused about the Exception part. When a exception occur...

1 comments posted 19yrs

posted by xing.starwill

1 comments posted 19yrs posted by xing.starwill

Mico32

G'day (o; As I started development on the Mico32 DSP board I've setup a site concentrating on my current work: - u-boot...

0 comments posted 19yrs

posted by me

0 comments posted 19yrs posted by me

Ph.D in France

Hi friends, I am working in the field of microelectronics particulary int the field FPGA's/mircontroller based products...

0 comments posted 19yrs

posted by mirzamihsan

0 comments posted 19yrs posted by mirzamihsan

Regional Clock Resources

Hi, I am having some trouble with implementing several serial links per IO Bank in Virtex5. An IO bank is about the sam...

1 comments posted 19yrs

posted by atodri

1 comments posted 19yrs posted by atodri

New Xilinx forum.

Hey Guys, Did any of you get an email like this last weekend(see below)? What a crock! Like a mug, I signed in tonight...

39 comments posted 19yrs

posted by symon_brewer

39 comments posted 19yrs posted by symon_brewer

Microblaze GPIO interrupt

I've hit a brick wall with this. I just can't figure out what I'm doing wrong, or not doing right! I just want to gener...

1 comments posted 19yrs

posted by markmcmahon

1 comments posted 19yrs posted by markmcmahon

EDK 8.1

All, We are desperately in need of EDK 8.1 for programming Xilinx Virtex-II MK325 . The disk we had is lost. Xilinx and...

3 comments posted 19yrs

posted by rukrimo

3 comments posted 19yrs posted by rukrimo

TEMAC Performance Issues with Virtex 4FX

Hello. I have designed a small application on a Virtex4FX based on the Xilinx lwIP Echo Server example ( www.files.em.a...

12 comments posted 19yrs

posted by ryufrank

12 comments posted 19yrs posted by ryufrank

Digilent USB module linux

Hello, I try to communicate with a Digilent S3- Board via USB-Module 2 using linux (libusb). Has anybody successfully tr...

1 comments posted 19yrs

posted by gauckler

1 comments posted 19yrs posted by gauckler

FPGA board connected to CMOS chip: ESD hazards?

I need to connect the Xilinx ML402 board to the 3.3V CMOS chip. I am concerned about the ESD that could burn the CMOS c...

5 comments posted 19yrs

posted by maricic

5 comments posted 19yrs posted by maricic

AREA_GROUP Map Error

I have a design that instantiates four copies of a module and I am using Xilinx's AREA_GROUP constraint to partition ea...

1 comments posted 19yrs

posted by mdhicks2

1 comments posted 19yrs posted by mdhicks2

Problem about clock switch in Quartus II 6.0

I use Cyclone II to implement image processing. There are a CMOS image sensor, a FPGA chip, and a SRAM on my board. I m...

4 comments posted 19yrs

posted by Xieyu1219

4 comments posted 19yrs posted by Xieyu1219

Exciting openings for Standard Cell libraries/Memory designer in a fortune 50 organisation

Hi All, This is Nitin Gupta from Itprogress. We are a Noida based executive search firm specializing in targetted searc...

0 comments posted 19yrs

posted by nitin74_gupta

0 comments posted 19yrs posted by nitin74_gupta

Need suggestion for my project

I am now preparing the project: encryption data stored in the SATA disk. I want to realize a device placed between the...

7 comments posted 19yrs

posted by xing.starwill

7 comments posted 19yrs posted by xing.starwill