Field-Programmable Gate Arrays

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Mico32 bootloader

Evnin' Not final but a small step before Lattice is ready with their Linux (o; http://www.mico32.org/archive/articles/mi...
0 comments posted 18yrs
posted by me
0 comments posted 18yrs posted by me

Virtex 4 IBUFG to DCM routing question

Hi all, Question on the clock routing in a Virtex 4 LX 25 that I haven't found the answer to today. I have an input clo...
9 comments posted 18yrs
posted by mikej
9 comments posted 18yrs posted by mikej

ChipHit: ASIC, FPGA, EDA Search Engine

Hi, I recently created a Google custom search engine called ChipHit at http://www.chiphit.com. Please take a look and p...
4 comments posted 18yrs
posted by ted.boydston
4 comments posted 18yrs posted by ted.boydston

Multiplication Problem on Microblaze Software

Hi, I want to do multiplication operation in my Microblaze's Test_Applicatio in Xilinx Plaform Studio. But i get some e...
16 comments posted 18yrs
posted by mfgunes
16 comments posted 18yrs posted by mfgunes

Xilinx PACKER warning bout carry

What does this "PACKER" warning mean? Lut _ driving carry _ can not be packed with the carry due to conflict with the c...
11 comments posted 18yrs
posted by bradsmallridge
11 comments posted 18yrs posted by bradsmallridge

System ACE failure on ML405

I keep running into a System ACE problem on the ML405 when trying to get my own ACE file to load. - I've properly forma...
3 comments posted 18yrs
posted by kunals.spam.account
3 comments posted 18yrs posted by kunals.spam.account

How to save simulation results in Xilinx ISE ?

Hi everyone, I am using Xilinx ISE simulator for behavioral simulation of a large circuit. I would like to save simulat...
1 comments posted 18yrs
posted by elet.mirror
1 comments posted 18yrs posted by elet.mirror

Xilinx DDR2 SDRAM controller performance

I am using the MIG generated DDR2 controller in a V5 device. The DDR2 runs at 266 MHz. I am meeting timing, but I am fi...
3 comments posted 18yrs
posted by bruce_hw_guy
3 comments posted 18yrs posted by bruce_hw_guy

Delaying a pulse train

I have to delay a pulse train by a given number of clocks on the same domain as the pulse to be delayed. The best appro...
21 comments posted 18yrs
posted by martin.usenet
21 comments posted 18yrs posted by martin.usenet

SDRAM Controller

Hi I have designed an SDRAM controller and nearly ready to synth and P&R. M question is do I need to add any offset con...
1 comments posted 18yrs
posted by maxascent
1 comments posted 18yrs posted by maxascent

Xilinx Spartan FPGA : Strange Errors

Hi, I wonder if anyone has seen something like this. I have an FPGA design targeted at an Spartan xc3s1500 and using IS...
5 comments posted 18yrs
posted by moogyd
5 comments posted 18yrs posted by moogyd

xst fails...

Hi, I'm currently trying to synthesize a big design on a Virtex4-VLX100. Now the problem is, that xst fails and just gi...
6 comments posted 18yrs
posted by REMOVEallesCAPITALS
6 comments posted 18yrs posted by REMOVEallesCAPITALS

mixed Verilog/VHDL in ispLever 7.0 broken

G'day (o; Just got the confirmation that ispLever 7.0 is broken for mixed Verilog/VHDL designs...my case was that a VHD...
2 comments posted 18yrs
posted by me
2 comments posted 18yrs posted by me

SATA OOB using Rocket IO (Virtex 5)

Hi All, Does anyone have information on using Rocket IO of Virtex 5 for SATA OOB. I would be grateful if anyone can sen...
0 comments posted 18yrs
posted by mkumarsampath
0 comments posted 18yrs posted by mkumarsampath