Xilinx blockram FIFO async reset annoys me (and Modelsim)

Hi all,

I'm facing a problem with Xilinx Coregen blockram fifo. At some point I want to reset it with a signal generated in a state machine. The reset makes the internal pointers in the FIFO to point to 0 address. However, the address stabilizes to 0 too late, right at the next rising edge of the clock that generated the reset signal. This produces a setup violation on the address port of the blockram.

I thought TRCE would detect the violation after my design is placed and routed, but this is not the case, not even setting the "ENABLE = reg_sr_q;" constraint in the UCF file.

I know my design will still work, and the output from the block cycle will remain in the unknown state only for one cycle, but I would like to correct it in a more elegant way. I don't want to see those warnings in modelsim anymore.

What approach would you suggest?

Thanks in advance.

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Frai
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