hi i am new to FPGA designs. i have a question about signal termination. the spartan 3e starter kit has a 10 ohm resistance in series and 10 pf capacitor to ground between CCLK pin of FPGA and CLK pin of Configuration PROM. i think this is for reducing signal reflection. Is it a good choice for doing this or do we need a parallel termination. and if we need a parallel termination then where it should be placed..on PROM end or FPGA end ? (master serial configuration) do we need termination for TCK signal if there is only a PROM and a FPGA in the chain ?
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16 years ago