Hi, I would like to create a system like below:
uBlaze customized IP uBlaze
Could anyone tell me whether it is possible to do that? Is there any constraint about the number of FSL pairs each customized IP can have?
I modified the .mpd by simply duplicating the ports'' names like below. I also duplicated the ports and HDL in IP''s HDL file. Then connecting the system like:
uBlaze_0 customized IP uBlaze_1
Synthesizing, par, generating Bitstream seem to be ok. while I have an error when I wanted to compile hello-world programs on both processors. Could anyone give me some advice that where can be the wrong part? Thanks a lot. David
=================================
BEGIN custom_ip
## Peripheral Options OPTION IPTYPE = PERIPHERAL OPTION IMP_NETLIST = TRUE OPTION HDL = VERILOG OPTION CORE_STATE = DEVELOPMENT OPTION IP_GROUP = MICROBLAZE:PPC:USER
## Bus Interfaces BUS_INTERFACE BUS = SFSL, BUS_TYPE = SLAVE, BUS_STD = FSL BUS_INTERFACE BUS = MFSL, BUS_TYPE = MASTER, BUS_STD = FSL BUS_INTERFACE BUS = S2, BUS_TYPE = SLAVE, BUS_STD = FSL BUS_INTERFACE BUS = M2, BUS_TYPE = MASTER, BUS_STD = FSL ## Generics for VHDL or Parameters for Verilog
## Ports PORT FSL_Clk = "", DIR = I, SIGIS = CLK, BUS = SFSL:MFSL PORT FSL_Rst = OPB_Rst, DIR = I, SIGIS = RST, BUS = SFSL:MFSL PORT FSL_S_Clk = FSL_S_Clk, DIR = O, SIGIS = Clk, BUS = SFSL PORT FSL_S_Read = FSL_S_Read, DIR = O, BUS = SFSL PORT FSL_S_Data = FSL_S_Data, DIR = I, VEC = [0:31], BUS = SFSL PORT FSL_S_Control = FSL_S_Control, DIR = I, BUS = MFSL PORT FSL_S_Exists = FSL_S_Exists, DIR = I, BUS = SFSL PORT FSL_M_Clk = FSL_M_Clk, DIR = O, SIGIS = Clk, BUS = MFSL PORT FSL_M_Write = FSL_M_Write, DIR = O, BUS = MFSL PORT FSL_M_Data = FSL_M_Data, DIR = O, VEC = [0:31], BUS = MFSL PORT FSL_M_Control = FSL_M_Control, DIR = O, BUS = MFSL PORT FSL_M_Full = FSL_M_Full, DIR = I, BUS = MFSL PORT FSL_Clk_2 = "", DIR = I, SIGIS = Clk, BUS = S2:M2 PORT FSL_Rst_2 = OPB_Rst, DIR = I, BUS = S2:M2, SIGIS = RST PORT FSL_S_Clk_2 = FSL_S_Clk_2, DIR = O, SIGIS = Clk, BUS = S2 PORT FSL_S_Read_2 = FSL_S_Read_2, DIR = O, BUS = S2 PORT FSL_S_Data_2 = FSL_S_Data_2, DIR = I, VEC = [0:31], BUS = S2 PORT FSL_S_Control_2 = FSL_S_Control_2, DIR = I, BUS = S2 PORT FSL_S_Exists_2 = FSL_S_Exists_2, DIR = I, BUS = S2 PORT FSL_M_Clk_2 = FSL_M_Clk_2, DIR = O, SIGIS = Clk, BUS = M2 PORT FSL_M_Write_2 = FSL_M_Write_2, DIR = O, BUS = M2 PORT FSL_M_Data_2 = FSL_M_Data_2, DIR = O, VEC = [0:31], BUS = M2 PORT FSL_M_Control_2 = FSL_M_Control_2, DIR = O, BUS = M2 PORT FSL_M_Full_2 = FSL_M_Full_2, DIR = I, BUS = M2
END