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flip-flop enable

Hi everyone, I'm experiencing something weird in my code implementation that leaded me to question which is the correct way to enable a flip-flop. Assuming I have a clocked output of a FF one cycle long (*en*) which will enable two different sequential logics according to the value of a signal *sel*, so *en1* and *en2* will be produced. Which is the best way to produce *en1* and *en2*?

When I designed the logic the first time I was doing something like this:

process (clk, nrst) begin if nrst = '0' then en1

Reply to
al.basili
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snipped-for-privacy@gmail.com schrieb:

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With the 1st solution you sample the signals en and sel. The outputs of the flipflops en1 and en2 are stable from the rising edge of clk to the next rising edge.

Meanwhile en and sel may be hazarderous. With the flipflop solution these hazards are no problem, but for the 2nd combinational solution this may be a problem.

Furthermore: If you use flipflops, then you break a timing path from the points where en and sel are driven to the points where en1 and en2 are read. With the flipflops you split this path into to paths.

Ralf

Reply to
Ralf Hildebrandt

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