Latest threads in Field-Programmable Gate Arrays

warning 1780 shown while synthesis, in xilinx 6.3i

hi I am designing a generic arbiter . while synthesis the xilinx tool is giving warning WARNING:Xst:646 - Signal is ass...

1 19yrs

ankurrawat0612

1 19yrs ankurrawat0612

vnavigator problem

Hello all, I am working on merging code coverage results in Verification Navigator from TransEDA. I am encountering an...

0 19yrs

kris.koorndyk

0 19yrs kris.koorndyk

Multiple CPLDs on a PCB.

Hi, Apologies if this isn't the best group, but there doesn't appear to be a comp.arch.cpld group. I'm going to start l...

13 19yrs

NickHolby

13 19yrs NickHolby

Actel Designer - Specifying multicycle path constraints (via .sdc file) when using synchronous clock enables

I have a design that uses a 100Mhz system clock, but only a very small portion actually runs at 100MHz. The rest of the...

1 19yrs

spdracer911

1 19yrs spdracer911

Import Xilinx SDK Project in Wind River Workbench

Hello, I would like to know if someone had already used the Wind River Workbench software to debug the PowerPC405 in th...

0 19yrs

lpaulo07

0 19yrs lpaulo07

ERROR:NgdBuild:604 with user ipcore

Hello, I created an ipcore opb2ip_bridge (with edk's wizard) interfacing the opb and added it to the edk reference desi...

6 19yrs

lars.schreiber

6 19yrs lars.schreiber

Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?

I was trying to estimate the power consumption of IGLOO AGL600V2 FPGA from Actel with IGLOO power calculator (posted on...

1 19yrs

ikogan

1 19yrs ikogan

Help on OCM BRAM intercafe and assembly code

Hello all:) I am having a problem with the OCM BRAM. I am using virtex II pro and EDK tools. I have an OCM BRAM and the...

0 19yrs

lastval

0 19yrs lastval

Help on ocm

Hello all:) I am having a problem with the OCM BRAM. I am using virtex II pro and EDK tools. I have an OCM BRAM and the...

0 19yrs

lastval

0 19yrs lastval

GTKWave 3.1.0 for win32

Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.1.0 which supports reload now. http://www.dspia.com...

0 19yrs

kal*

0 19yrs kal*

[Nios II] How Can I define the pio inputs as a interrupt?

I use the Nios II system to achieve my design. I have define a data bus from the outside of the FPGA, I use a 8-bits PI...

2 19yrs

hezhikuan2007

2 19yrs hezhikuan2007

Low-level FPGA programming?

Hi. It is possible to have a format of .pof/.sof files from Altera, thus, to decompile some ready projects and try to ma...

5 19yrs

drop669

5 19yrs drop669

Cannot pass par in tcl, Xilinx webpack 9.1.

Hi, I am learning tcl in Xilinx 9.1. For the learning example watchvhd, the following error occurs. ERROR:Portability:9...

0 19yrs

rxjwg98

0 19yrs rxjwg98

Beginning FPGA programming

I'd like to try out some ideas and would appreciate some guidance. Would a 200k-gate FPGA be enough for a simple or com...

14 19yrs

james.harris.1

14 19yrs james.harris.1

opb_timer interrupt self test problem

Hello there! I ported the WebServer example from MicroBlaze Development Kit, Spartan -3E 1600E Edition to spartan 3e st...

2 19yrs

dormanpeter1

2 19yrs dormanpeter1

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