Field-Programmable Gate Arrays

Multiple CPLDs on a PCB.

Hi, Apologies if this isn't the best group, but there doesn't appear to be a comp.arch.cpld group. I'm going to start l...

13 comments posted 18yrs

posted by NickHolby

13 comments posted 18yrs posted by NickHolby

Actel Designer - Specifying multicycle path constraints (via .sdc file) when using synchronous clock enables

I have a design that uses a 100Mhz system clock, but only a very small portion actually runs at 100MHz. The rest of the...

1 comments posted 18yrs

posted by spdracer911

1 comments posted 18yrs posted by spdracer911

Import Xilinx SDK Project in Wind River Workbench

Hello, I would like to know if someone had already used the Wind River Workbench software to debug the PowerPC405 in th...

0 comments posted 18yrs

posted by lpaulo07

0 comments posted 18yrs posted by lpaulo07

ERROR:NgdBuild:604 with user ipcore

Hello, I created an ipcore opb2ip_bridge (with edk's wizard) interfacing the opb and added it to the edk reference desi...

6 comments posted 18yrs

posted by lars.schreiber

6 comments posted 18yrs posted by lars.schreiber

Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?

I was trying to estimate the power consumption of IGLOO AGL600V2 FPGA from Actel with IGLOO power calculator (posted on...

1 comments posted 18yrs

posted by ikogan

1 comments posted 18yrs posted by ikogan

Help on OCM BRAM intercafe and assembly code

Hello all:) I am having a problem with the OCM BRAM. I am using virtex II pro and EDK tools. I have an OCM BRAM and the...

0 comments posted 18yrs

posted by lastval

0 comments posted 18yrs posted by lastval

Help on ocm

Hello all:) I am having a problem with the OCM BRAM. I am using virtex II pro and EDK tools. I have an OCM BRAM and the...

0 comments posted 18yrs

posted by lastval

0 comments posted 18yrs posted by lastval

GTKWave 3.1.0 for win32

Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.1.0 which supports reload now. http://www.dspia.com...

0 comments posted 18yrs

posted by kal*

0 comments posted 18yrs posted by kal*

[Nios II] How Can I define the pio inputs as a interrupt?

I use the Nios II system to achieve my design. I have define a data bus from the outside of the FPGA, I use a 8-bits PI...

2 comments posted 18yrs

posted by hezhikuan2007

2 comments posted 18yrs posted by hezhikuan2007

Low-level FPGA programming?

Hi. It is possible to have a format of .pof/.sof files from Altera, thus, to decompile some ready projects and try to ma...

5 comments posted 18yrs

posted by drop669

5 comments posted 18yrs posted by drop669

Cannot pass par in tcl, Xilinx webpack 9.1.

Hi, I am learning tcl in Xilinx 9.1. For the learning example watchvhd, the following error occurs. ERROR:Portability:9...

0 comments posted 18yrs

posted by rxjwg98

0 comments posted 18yrs posted by rxjwg98

Beginning FPGA programming

I'd like to try out some ideas and would appreciate some guidance. Would a 200k-gate FPGA be enough for a simple or com...

14 comments posted 18yrs

posted by james.harris.1

14 comments posted 18yrs posted by james.harris.1

opb_timer interrupt self test problem

Hello there! I ported the WebServer example from MicroBlaze Development Kit, Spartan -3E 1600E Edition to spartan 3e st...

2 comments posted 18yrs

posted by dormanpeter1

2 comments posted 18yrs posted by dormanpeter1

V5 Configuration via SPI

Hi *, on one of our next boards, I'd like to use the Virtex5 feature to have it program itself from an external SPI fla...

6 comments posted 18yrs

posted by news_sep07

6 comments posted 18yrs posted by news_sep07

flip-flop enable

Hi everyone, I'm experiencing something weird in my code implementation that leaded me to question which is the correct...

1 comments posted 18yrs

posted by al.basili

1 comments posted 18yrs posted by al.basili