warning 1780 shown while synthesis, in xilinx 6.3i

hi I am designing a generic arbiter . while synthesis the xilinx tool is giving warning

WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned.

I searched it out in the solution record warning 646 can be ignored . but warning 1780 is displayed in the case of jtag ,so i am not able to conceive why this is coming. i have pasted the design below. thanks for help ankur

module pri_encoder32(inbus,outbus);

parameter size=9; parameter size_1=size-1; parameter size_out=4; input [size-1:0]inbus;

output reg [size_out-1:0]outbus;

reg [size_out-1:0]k; reg [size_out-1:0]inter;

always @(inbus) begin inter=0; for (k = size; k >= 1; k = k - 1) begin

if (inbus[k-1]==1) begin outbus = k-1; inter=k-1; end else begin outbus=inter; end end

end

endmodule