I use the Nios II system to achieve my design. I have define a data bus from the outside of the FPGA, I use a 8-bits PIO ip to connect the signal and the FPGA.
I want to achieve the following aim: when the outside signals changes, Nios generates a IRQ to CPU, and I can insert my instructions.
Please tell me , how can I do it ?
Read Chapter 13 of the QUartus II Handbook Volume 5. (aka n2cpu_nii51007-2.pdf)
Or if that's not quite what you need, create a (trivial) SOPC component that generates an interrupt when you need to.
Regards,
Thank you very much! You give me a lot!
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