Low-level FPGA programming?

No, we do not give out the format of the POF/SOF.

Sorry,

Paul Leventis Altera Corp.

BTW, is the same possible with Xilinx?

It would be theoretically possible, but definitley a non-trivial exercise.

You've probably noticed the variation in pof/sof size depending on the target chip? You could start by trying various combinations of logic, with forced placement in the same area on the FPGA and see how it changes the format of the pof/sof file. Similarly, repeat the same logic combinations in different areas, and look for repeating pattern in the pof/sof files.

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Why bother when the tools are (basically) free from ALTERA , and of a very high quality anyway? (imho)

Red

Just a quick follow up to this posting, I didn't want to say anything more until I knew more about.

I have finally been able to confirm with Xilinx that "data files generated by the Software" is not intended to include XDL files.

Austin: Thanks for helping me get in touch with the right people.

/Andreas

It appears to be back now.

- a