I have a design that uses a 100Mhz system clock, but only a very small portion actually runs at 100MHz. The rest of the FFs in the design use a synchronous "clk_10M_en" signal which is active for one clock period and repeats every 100ns. I would like to know how to specify the constraints correctly so that Actel Designer (i.e. SmartTime)) knows "that paths FROM FFs using clk_10M_en TO FFs using clk_10M_en" are 100ns paths, not 10ns paths.
It's quiet easy to add a multicycle path constraint on the two registers, such as:
set_multicycle_path 10 -from {reg1:CLK} -to {reg2:CLK}
But what I need is a solution that can find these registers when they are buried in a hierarchy of modules. Since they all use clk_10M_en as their enable, there should be a way to perform a "find" and then set a multicycle path constraint between each regsiter.
I have contacted Actel but they refer me to their docs or using the GUI tools which does not solve my problem. Surely this can be done via the .sdc constraints file using some TCL code.
TIA.
David