ERROR:NgdBuild:604 with user ipcore

Hello,

I created an ipcore opb2ip_bridge (with edk's wizard) interfacing the opb and added it to the edk reference design. So far, so good. While running generate bitstream, synthesis stage runs through, but implementation stage aborts immediately with ERROR:NgdBuild:604.

--------------------------- logfile excerpt: ERROR:NgdBuild:604 - logical block 'opb2ip_bridge_0/opb2ip_bridge_0/USER_LOGIC_I/moduleA_0' with type 'moduleA' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'moduleA' is not supported in target 'virtex2p'.

ERROR:NgdBuild:604 - logical block 'opb2ip_bridge_0/opb2ip_bridge_0/USER_LOGIC_I/moduleB_0' with type 'moduleB' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'moduleB' is not supported in target 'virtex2p'.

---------------------------

My userdefined ipcore is unitized in a hierarchy of vhdl modules like:

-opb2ip_bridge |-USER_LOGIC ||-moduleA ||-moduleB |||-moduleA

Could this be the reason for the error. If so, is there any configuration file, I would have to modify previously to make the synthesis/ implementation stage be aware that my ipcore is designed modular and how to resolve the symbol names.

Or what is the real problem and how do I have to solve it.

I'm working under edk and ise version 8 and latest service packs. The reference design is not the problem, because it's already working in other designs.

Thanks for you help. Greetings, Lars.

Reply to
L. Schreiber
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Hello,

I created an ipcore opb2ip_bridge (with edk's wizard) interfacing the opb and added it to the edk reference design. So far, so good. While running generate bitstream, synthesis stage runs through, but implementation stage aborts immediately with ERROR:NgdBuild:604.

--------------------------- logfile excerpt: ERROR:NgdBuild:604 - logical block 'opb2ip_bridge_0/opb2ip_bridge_0/USER_LOGIC_I/moduleA_0' with type 'moduleA' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'moduleA' is not supported in target 'virtex2p'.

ERROR:NgdBuild:604 - logical block 'opb2ip_bridge_0/opb2ip_bridge_0/USER_LOGIC_I/moduleB_0' with type 'moduleB' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'moduleB' is not supported in target 'virtex2p'.

---------------------------

My userdefined ipcore is unitized in a hierarchy of vhdl modules like:

-opb2ip_bridge |-USER_LOGIC ||-moduleA ||-moduleB |||-moduleA

Could this be the reason for the error. If so, is there any configuration file, I would have to modify previously to make the synthesis/ implementation stage be aware that my ipcore is designed modular and how to resolve the symbol names.

Or what is the real problem and how do I have to solve it.

I'm working under edk and ise version 8 and latest service packs. The reference design is not the problem, because it's already working in other designs.

Thanks for you help. Greetings, Lars.

Reply to
L. Schreiber

I've seen something similar with COREgen modules in mixed language designs. Is moduleB a black box? Do you have a .ngc file created for moduleB? Is it in the project directory?

If you answer yes to all three questions, then there is the possibility that ISE is looking for your .ngc code in another file such as moduleB_0.ngc due to the hierarchy created. In that case copying moduleB.ngc to moduleB_0.ngc can fix the problem.

The same would apply to moduleA.

HTH, Gabor

Reply to
Gabor

No, it's a vhdl only design.

No, there are no black-box attributed instances inside the peripheral ip design.

No, it doesn't seem, that the edk has built ngc files for the submodules of the ip while executing "generate bitstreams" . Inside the implementations directory there is only a opb2ip_0_wrapper.ngc for the toplevel of my ipcore besides all the ngc files from the reference design.

My ip lies inside an external ip repository and is linked into the edk reference design project.

Reply to
L. Schreiber

Is your moduleA and moduleB listed in the PAO file? If is not listed in the PAO, then it will not synthesized by XST. Xst will give a warning that the moduleA and moduleB are black box components.

Take a looke at you /synthesis/> Gabor schrieb:

Reply to
Paulo Dutra

Exactly, this was the problem, I found out yesterday late afternoon, too. :-D

Thanks anyway. So I don't need to write the solution anymore.

Reply to
L. Schreiber

OK, I have corrected this error, I found the main problem is that the project can not find where the "black box" is, this means you should add your "black box" into the project library, and then rerun synthesize, lastly implement design.

Reply to
ARRON

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